80C286_08 Datasheet, PDF (32/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
CLK
MEMORY CYCLE N - 1
T_S
φ1
φ2
T_C
φ1
φ2
PROC
CLK
A₂₃ - A₀
VALID ADDR
S0 • S1
T_S
φ1
φ2
MEMORY CYCLE N
T_C
φ1
φ2
T_C
φ1
φ2
VALID ADDR
VALID ADDR
SRDY
READY
(SEE NOTE 8)
(SEE NOTE 9)
ARDY
(SEE NOTE 10)
NOTES:
8. SRDYEN is active low.
9. If SRDYEN is high, the state of SRDY will not effect READY.
10. ARDYEN is active low.
FIGURE 24. SYNCHRONOUS AND ASYNCHRONOUS READY
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