80C286_08 Datasheet, PDF (36/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
BUS CYCLE TYPE
CLK
HOLD
BUS HOLD ACKNOWLEDGE
T_H
φ1 φ2
T_H
φ1 φ2
T_H
φ1 φ2
T_S
φ1 φ2
WRITE CYCLE
T_C
φ1 φ2
T_C
φ1 φ2
T_C
φ1 φ2
BUS HOLD
ACKNOWLEDGE
T_I
φ1 φ2
T_H
φ1 φ2
(SEE NOTE 14)
(SEE NOTE 15)
(SEE NOTE 16)
HLDA
(SEE NOTE 11)
S1 • S0
A₂₃ - A₀
M/IO,
COD/INTA
BHE, LOCK
VALID
VALID
(SEE NOTE 12)
(SEE NOTE 13)
(SEE NOTE 11)
D₁₅ - D₀
SRDY +
SRDYEN
ARDY +
ARDYEN
CMDLY
MWTC
V_OH
DT/R
DEN
VALID
NOT READY NOT READY (SEE NOTE 17)
NOT READY NOT READY
READY
DELAY ENABLE
(SEE NOTE 17)
ALE
T_S - STATUS CYCLE
T_C - COMMAND CYCLE
NOTES:
11. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.
12. Address, M/IO and COD/lNTA may start floating during any T_C depending on when internal 80C286 bus arbiter decides to release bus
to external HOLD. The float starts in φ2 of T_C.
13. BHE and LOCK may start floating after the end of any T_C depending on when internal 80C286 bus arbiter decides to release bus to
external HOLD. The float starts in φ1 of T_C.
14. The minimum HOLD to HLDA time is shown. Maximum is one T_H longer.
15. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
16. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,
Interrupts, Waits, Lock, etc.).
17. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state
is ignored after ready is signaled via the asynchronous input.
FIGURE 28. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD
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