80C286_08 Datasheet, PDF (4/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
Pin Descriptions The following pin function descriptions are for the 80C286 microprocessor.
SYMBOL
CLK
PIN
NUMBER
31
D₁₅ - D₀
36 - 51
A₂₃ - A₀
BHE
7-8
10 - 28
32 - 43
1
TYPE
I
I/O
O
O
DESCRIPTION
SYSTEM CLOCK: provides the fundamental timing for the 80C286 system. It is divided by two inside
the 80C286 to generate the processor clock. The internal divide-by-two circuitry can be synchro-
nized to an external clock generator by a LOW to HIGH transition on the RESET input.
DATA BUS: inputs data during memory, I/O, and interrupt acknowledge read cycles; outputs data
during memory and I/O write cycles. The data bus is active HIGH and is held at high impedance to
the last valid logic level during bus hold acknowledge.
ADDRESS BUS: outputs physical memory and I/O port addresses. A₂₃ - A₁₆ are LOW during I/O
transfers. A₀ is LOW when data is to be transferred on pins D₇ - D₀ (see table below). The address
bus is active High and floats to three-state off during bus hold acknowledge.
BUS HIGH ENABLE: indicates transfer of data on the upper byte of the data bus, D₁₅ - D₈. Eight-bit
oriented devices assigned to the upper byte of the data bus would normally use BHE to condition chip
select functions. BHE is active LOW and floats to three-state OFF during bus hold acknowledge.
BHE AND A₀ ENCODINGS
BHE VALUE
0
A₀ VALUE
0
Word transfer
FUNCTION
0
1
Byte transfer on upper half of data bus (D₁₅ - D₈)
1
0
Byte transfer on lower half of data bus (D₇ - D₀)
1
1
Reserved
S1, S0
4, 5
O
BUS CYCLE STATUS: indicates initiation of a bus cycle and along with M/IO and COD/lNTA, de-
fines the type of bus cycle. The bus is in a T_S state whenever one or both are LOW. S1 and S0 are
active LOW and are held at a high impedance logic one during bus hold acknowledge.
80C286 BUS CYCLE STATUS DEFINITION
COD/INTA M/IO S1
0(LOW)
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1(HIGH)
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
S0
BUS CYCLE INITIATED
0 Interrupt acknowledge
1 Reserved
0 Reserved
1 None; not a status cycle
0 If A₁ = 1 then halt; else shutdown
1 Memory data read
0 Memory data write
1 None; not a status cycle
0 Reserved
1 I/O read
0 I/O write
1 None; not a status cycle
0 Reserved
1 Memory instruction read
0 Reserved
1 None; not a status cycle
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