80C286_08 Datasheet, PDF (18/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
TABLE 10. CODE AND DATA SEGMENT DESCRIPTOR FORMATS - ACCESS RIGHTS BYTE DEFINITION
BIT
POSITION
NAME
FUNCTION
7
Present (P)
P = 1 Segment is mapped into physical memory.
P = 0 No mapping to physical memory exits, base and limit are not used.
6-5
Descriptor Privilege
Level (DPL)
Segment privilege attribute used in privilege tests.
4
Segment Descriptor (S) S = 1 Code or Data (includes stacks) segment descriptor
S = 0 System Segment Descriptor or Gate Descriptor
3
Executable (E)
E = 0 Data segment descriptor type is:
2
Expansion Direction ED = 0 Expand up segment, offsets must be ≤ limit.
(ED)
ED = 1 Expand down segment, offsets must be > limit.
1
Writable (W)
W = 0 Data segment may not be written into.
If Data Segment
(S = 1, E = 0)
W = 1 Data segment may be written into.
Type
3
Executable (E)
Field
Definition
2
Conforming (C)
1
Readable (R)
E=1
C=1
R=0
Code Segment Descriptor type is:
Code segment may only be executed when CPL ≥
DPL and CPL remains unchanged.
Code segment may not be read.
If Code Segment
(S = 1, E = 1)
R = 1 Code segment may be read.
0
Accessed (A)
A = 0 Segment has not been accessed.
A=1
Segment selector has been loaded into segment register or used by selector
test instructions.
18