80C286_08 Datasheet, PDF (21/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
CPU
15
0
23 ^{GDT LIMIT}
GDT BASE
24-BIT PHYS AD
15
0
LDT
DESCR
SELECTOR
15
0
23 ^{LDT LIMIT}
LDT BASE
24-BIT PHYS AD
PROGRAM INVISIBLE
(AUTOMATICALLY
LOADED
FROM LDT DESCR
WITHIN GDT)
MEMORY
GDT
LDT₁
CURRENT
LDT
LDT_n
FIGURE 14. LOCAL AND GLOBAL DESCRIPTOR TABLE
DEFINITION
The LGDT and LLDT instructions load the base and limit of
the global and local descriptor tables. LGDT and LLDT are
privileged, i.e. they may only be executed by trusted pro-
grams operating at level 0. The LGDT instruction loads a six
byte field containing the 16-bit table limit and 24-bit physical
base address of the Global Descriptor Table as shown in
Figure 15. The LDT instruction loads a selector which refers
to a Local Descriptor Table descriptor containing the base
address and limit for an LDT, as shown in Table 11.
7
07
0
+5
RESERVED †
BASE _{23 - 16}
+4
+3
BASE _{15 - 0}
+2
+1
LIMIT _{15 - 0}
0
15
87
0
† MUST BE SET TO 0 FOR COMPATIBILITY WITH FUTURE UPGRADES
FIGURE 15. GLOBAL DESCRIPTOR TABLE AND INTERRUPT
DESCRlPTOR TABLE DATA TYPE
Interrupt Descriptor Table
The protected mode 80C286 has a third descriptor table,
called the Interrupt Descriptor Table (IDT) (see Figure 16),
used to define up to 256 interrupts. It may contain only task
gates, interrupt gates and trap gates. The IDT (Interrupt
Descriptor Table) has a 24-bit physical base and 16-bit limit
register in the CPU. The privileged LlDT instruction loads
these registers with a six byte value of identical form to that
of the LGDT instruction (see Figure 16 and Protected Mode
lnitialization).
References to IDT entries are made via INT instructions, exter-
nal interrupt vectors, or exceptions. The IDT must be at least
256 bytes in size to allocate space for all reserved interrupts.
CPU
15
0
IDT LIMIT
IDT BASE
23
0
MEMORY
GATE FOR
INTERRUPT #n
GATE FOR
INTERRUPT #n-1
GATE FOR
INTERRUPT #1
GATE FOR
INTERRUPT #0
INTERRUPT
DESCRIPTOR
TABLE
(IDT)
FIGURE 16. INTERRUPT DESCRIPTOR TABLE DEFINITION
Privilege
The 80C286 has a four-level hierarchical privilege system
which controls the use of privileged instructions and access
to descriptors (and their associated segments) within a task.
Four-level privilege, as shown in Figure 17, is an extension
of the users/supervisor mode commonly found in minicom-
puters. The privilege levels are numbered 0 through 3. Level
0 is the most privileged level. Privilege levels provide protec-
tion within a task. (Tasks are isolated by providing private
LDT’s for each task.) Operating system routines, interrupt
handlers, and other system software can be included and
protected within the virtual address space of each task using
the four levels of privilege. Each task in the system has a
separate stack for each of its privilege levels.
Tasks, descriptors, and selectors have a privilege level
attribute that determines whether the descriptor may be
used. Task privilege affects the use of instructions and
descriptors. Descriptor and selector privilege only affect
access to the descriptor.
CPU
ENFORCED
SOFTWARE
INTERFACES
APPLICATIONS
HIGH SPEED
OPERATING
SYSTEM
INTERFACE
OS EXTENSIONS
PL = 3
SYSTEM
SERVICES
PL = 2
PL = 1
KERNAL
PL = 0
MOST
PRIVILEGED
NOTE: PL becomes numerically lower as privilege level increases.
FIGURE 17. HIERARCHICAL PRIVILEGE LEVELS
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