80C286_08 Datasheet, PDF (27/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
synchronizes READY and RESET. The 82C288 converts
bus operation status encoded by the 80C286 into command
and bus control signals. The 82289 bus arbiter generates
Multibus™ bus arbitration signals. These components can
provide the critical timing required for most system bus inter-
faces including the Multibus.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices, and to eliminate the need for pull-up/down
resistors, “bus-hold” circuitry has been used on the 80C286
pins 4-6, 36-51 and 66-68 (See Figure 19A and 19B). The
circuit shown in Figure 19A will maintain the last valid logic
state if no driving source is present (i.e. an unconnected pin
or a driving source which goes to a high impedance state).
The circuit shown in Figure 19B will maintain a high imped-
ance logic one state if no driving source is present. To over-
drive the “bus-hold” circuits, an external driver must be
capable of sinking or sourcing approximately 400 microamps
at valid input voltage levels. Since this “bus-hold” circuitry is
active and not a “resistive” type element, the associated
power supply current is negligible, and power dissipation is
significantly reduced when compared to the use of passive
pull-up resistors.
OUTPUT
DRIVER
BOND
PAD
EXTERNAL
PIN
INPUT
DRIVER
INPUT
PROTECTION
CIRCUITRY
address. Byte transfers occur on either half of the 16-bit local
data bus. Even bytes are accessed over D_7-0 while odd bytes
are transferred over D_15-8. Even addressed words are trans-
ferred over D_15-0 in one bus cycle, while odd addressed word
require two bus operations. The first transfers data on D_15-8,
and the second transfers data on D_7-0. Both byte data trans-
fers occur automatically, transparent to software.
Two bus signals, A₀ and BHE, control transfers over the
lower and upper halves of the data bus. Even address byte
transfers are indicated by A₀ LOW and BHE HIGH. Odd
address byte transfers are indicated by A₀ HlGH and BHE
LOW. Both A₀ and BHE are LOW for even address word
transfers.
The I/O address space contains 64K addresses in both
modes. The I/O space is accessible as either bytes or words,
as is memory. Byte wide peripheral devices may be attached
to either the upper or lower byte of the data bus. Byte-wide I/O
devices attached to the upper data byte (D_15-8) are accessed
with odd I/O addresses. Devices on the lower data byte are
accessed with even I/O addresses. An interrupt controller
such as Intersil's 82C59A must be connected to the lower
data byte (D_7-0) for proper return of the interrupt vector.
Bus Operation
The 80C286 uses a double frequency system clock (CLK
input) to control bus timing. All signals on the local bus are
measured relative to the system CLK input. The CPU divides
the system clock by 2 to produce the internal processor
clock, which determines bus state. Each processor clock is
composed of two system clock cycles named phase 1 and
phase 2. The 82C284 clock generator output (PCLK) identi-
fies the next phase of the processor clock. (See Figure 20.)
FIGURE 19A. BUS HOLD CIRCUITRY, PINS 36-51, 66, 67
OUTPUT
DRIVER
V_CC
P
BOND
PAD
EXTERNAL
PIN
CLK
PCLK
ONE PROCESSOR CLOCK CYCLE
ONE BUS T STATE
PHASE 1
OF PROCESSOR
CLOCK CYCLE
PHASE 2
OF PROCESSOR
CLOCK CYCLE
ONE SYSTEM
CLK CYCLE
INPUT
DRIVER
INPUT
PROTECTION
CIRCUITRY
FIGURE 20. SYSTEM AND PROCESSOR CLOCK RELATION-
SHIPS
Six types of bus operations are supported; memory read,
memory write, I/O read, I/O write, interrupt acknowledge,
and halt/shutdown. Data can be transferred at a maximum
rate of one word per two processor clock cycles.
FIGURE 19B. BUS HOLD CIRCUITRY, PINS 4-6, 68
Physical Memory and I/O Interface
A maximum of 16 megabytes of physical memory can be
addressed in protected mode. One megabyte can be
addressed in real address mode. Memory is accessible as
bytes or words. Words consist of any two consecutive bytes
addressed with the least significant byte stored in the lowest
The 80C286 bus has three basic states: idle (T_I), send sta-
tus (T_S), and perform command (T_C). The 80C286 CPU also
has a fourth local bus state called hold (T_H). T_H indicates
that the 80C286 has surrendered control of the local bus to
another bus master in response to a HOLD request.
Each bus state is one processor clock long. Figure 21 shows
the four 80C286 local bus states and allowed transitions.
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