80C286_08 Datasheet, PDF (48/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
Waveforms (Continued)
BUS CYCLE TYPE
CLK
PCLK
(SEE NOTE 47)
INTR, NMI
HOLD, PEREQ
(SEE NOTE 45)
4
ERROR, BUSY
(SEE NOTE 46)
V_CH
T_X
φ1
φ2
V_{CL 19}
19
4
5
5
V_CH
φ2
CLK
V_CL
RESET
V_CH
CLK
V_CL
RESET
φ1 ^TX
φ2
φ1
(SEE NOTE 47)
7
6
T_X
φ1
φ2
φ1
7
(SEE NOTE 47)
6
FIGURE 35. 80C286 ASYNCHRONOUS INPUT SIGNAL TIMING
NOTES:
45. PCLK indicates which processor cycle phase will occur on the
next CLK, PCLK may not indicate the correct phase until the first
cycle is performed.
46. These inputs are asynchronous. The setup and hold times
shown assure recognition for testing purposes.
FIGURE 36. 80C286 RESET INPUT TIMING AND SUBSEQUENT
PROCESSOR CYCLE PHASE
NOTE:
47. When RESET meets the setup time shown, the next CLK will
start or repeat φ1 of a processor cycle.
48