80C286_08 Datasheet, PDF (26/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
CPU
TASK REGISTER
TR
15
0
PROGRAM INVISIBLE
15
0
LIMIT
BASE
23
0
SYSTEM
SEGMENT
DESCRIPTOR
RESERVED
P D 0 TYPE
P
L
BASE _{23 - 16}
BASE _{15 - 0}
LIMIT _{15 - 0}
TYPE
DESCRIPTION
1 An available task state segment.
May be used as the destination
of a task switch operation.
3 A busy task state segment. Can-
not be used as the destination of
a task switch.
TASK
STATE
SEGMENT
15
TASK LDT SELECTOR
BYTE
0 _OFFSET
42
DS SELECTOR
SS SELECTOR
CS SELECTOR
ES SELECTOR
DI
40
P
DESCRIPTION
38
1 Base and Limit fields are valid.
36
0 Segment is not present in mem-
34
ory, Base and Limit are not de-
32
fined.
SI
30
BP
28 ^CURRENT
TASK
SP
26 STATE
BX
24
DX
22
CX
20
AX
18
FLAG WORD
16
IP (ENTRY POINT)
14
SS FOR CPL 2
12
SP FOR CPL 2
10
SS FOR CPL 1
SP FOR CPL 1
SS FOR CPL 0
8 INITIAL
STACKS
6 _{FOR CPL 0, 1, 2}
4
SP FOR CPL 0
2
BACK LINK SELECTOR TO TSS 0
FIGURE 18. TASK STATE SEGMENT AND TSS REGISTERS
System Interface
The 80C286 system interface appears in two forms: a local
bus and a system bus. The local bus consists of address,
data, status, and control signals at the pins of the CPU. A sys-
tem bus is any buffered version of the local bus. A system bus
may also differ from the local bus in terms of coding of status
and control lines and/or timing and loading of signals.
Bus Interface Signals and Timing
The 80C286 microsystems local bus interfaces the 80C286 to
local memory and I/O components. The interface has 24
address lines, 16 data lines, and 8 status and control signals.
The 80C286 CPU, 82C284 clock generator, 82C288 bus
controller, 82289 bus arbiter, 82C86H/87H transceivers, and
82C82/83H latches provide a buffered and decoded system
bus interface. The 82C284 generates the system clock and
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