80C286_08 Datasheet, PDF (11/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
Memory Organization
Memory is organized as sets of variable-length segments. Each
segment is a linear contiguous sequence of up to 64K (2¹⁶) 8-
bit bytes. Memory is addressed using a two-component
address (a pointer) that consists of a 16-bit segment selector
and a 16-bit offset. The segment selector indicates the desired
segment in memory. The offset component indicates the
desired byte address within the segment. (See Figure 3).
All instructions that address operands in memory must spec-
ify the segment and the offset. For speed and compact
instruction encoding, segment selectors are usually stored in
the high speed segment registers. An instruction need spec-
ify only the desired segment register and offset in order to
address a memory operand.
POINTER
SEGMENT
OFFSET
31
16 15
0
OPERAND
SELECTED
SELECTED
SEGMENT
Addressing Modes
The 80C286 provides a total of eight addressing modes for
instructions to specify operands. Two addressing modes are
provided for instructions that operate on register or immedi-
ate operands:
REGISTER OPERAND MODE: The operand is located in
one of the 8 or 16-bit general registers.
IMMEDIATE OPERAND MODE: The operand is included in
the instruction.
Six modes are provided to specify the location of an operand in
a memory segment. A memory operand address consists of
two 16-bit components: segment selector and offset. The seg-
ment selector is supplied by a segment register either implicitly
chosen by the addressing mode or explicitly chosen by a seg-
ment override prefix. The offset is calculated by summing any
combination of the following three address elements:
the displacement (an 8 or 16-bit immediate value contained
in the instruction)
the base (contents of either the BX or BP base registers)
the index (contents of either the SI or Dl index registers)
MEMORY
FIGURE 3. TWO COMPONENT ADDRESS
Most instructions need not explicitly specify which segment
register is used. The correct segment register is automati-
cally chosen according to the rules of Table 3. These rules
follow the way programs are written (see Figure 4) as inde-
pendent modules that require areas for code and data, a
stack, and access to external data areas.
Special segment override instruction prefixes allow the
implicit segment register selection rules to be overridden for
special cases. The stack, data and extra segments may
coincide for simple programs. To access operands not resid-
ing in one of the four immediately available segments, a full
32-bit pointer or a new segment selector must be loaded.
TABLE 3. SEGMENT REGISTER SELECTION RULES
MEMORY SEGMENT
REFERENCE REGISTER
NEEDED
USED
IMPLICIT SEGMENT
SELECTION RULE
MODULE A
CODE
DATA
MODULE B
CODE
DATA
PROCESS
STACK
PROCESS
DATA
BLOCK 1
CPU
CODE
DATA
STACK
EXTRA
SEGMENT
REGISTERS
Instructions
Stack
Code (CS) Automatic with instruction prefetch
Stack (SS) All stack pushes and pops. Any
memory reference which uses BP
as a base register.
PROCESS
DATA
BLOCK 2
Local Data
External
(Global) Data
Data (DS) All data references except when
relative to stack or string destination
Extra (ES) Alternate data segment and
destination of string operation
MEMORY
FIGURE 4. SEGMENTED MEMORY HELPS STRUCTURE
SOFTWARE
Any carry out from the 16-bit addition is ignored. Eight-bit
displacements are sign extended to 16-bit values.
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