GW80314GSSL7NK Datasheet, PDF (9/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Introduction
1.0
Introduction
Figure 1.
This is the Intel^® GW80314 I/O Processor Datasheet. This document contains a functional
overview, package signal locations, targeted electrical specifications, and bus functional
waveforms. Detailed functional descriptions other than parametric performance are published in
the Intel^® GW80314 I/O Processor Developer Manual.
Figure 1 shows a block diagram.
Intel^® GW80314 I/O Processor Block Diagram
32-bit Address / 64-bit Data
100 MHz Operation
JTAG
Intel^® 80200
Bus Interface
DMA
CRC32C
XOR
PCI-X
PCI-X
SRAM
Switching
Fabric
Registers
DDR
Interface
10/100/1G
Ethernet
4 Timers
Interrupt
Controller
I²C UARTs
Host
Port
4 Chip
Selects
B1342-01
This bridge is designed as a fabric centric, any-port-to-any-port bridge. All transactions are placed
into fabric packets and routed via address-based port selection to another fabric port. The bridge is
based on the “store and forward” concept, where transactions are buffered at the incoming port.
When a packet is complete, the incoming port knows the size of the packet, and it can be burst
across the fabric to the outgoing port. As the timing of the packet is deterministic at the outgoing
port, the transaction can be started at the outgoing port as soon as the header arrives. All outgoing
Datasheet
9