GW80314GSSL7NK Datasheet, PDF (22/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
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3.1.4
Dual-Gigabit Ethernet (GigE) Interface Signals
This section describes signals for the GW80314 dual-ethernet controller. Signals in this group are
3.3 V LVTTL compatible.
Table 6.
GigE Signals (Sheet 1 of 3)
Pin Name
Count Pin Type
Description
Port 0
E0_TCG[3:0]
E0_TCG[7:4]
E0_TCG[8]
E0_TCG[9]
E0_RCG[3:0]
E0_RCG[7:4]
E0_RCG[8]
E0_RCG[9]
E0_PCRS_SDET
E0_PCOL_RBCM
E0_ECMDT
E0_EWRAP
E0_PRBSEN
E0_PRBS_PASS
4
TO All modes: Transmit Code Group Lower Nibble.
4
TO GMII mode: Transmit Code Group Upper Nibble.
TBI mode: Transmit Code Group Upper Nibble.
1
TO MII mode: Transmit Enable. This signal is synchronous to E0_TX_CLK and
provides precise framing for data carried on E0_TCG[3:0] for the external
PMA. It is asserted when E0_TCG[3:0] contains valid data to be transmitted.
G/MII mode: Transmit Enable. This signal is synchronous to GTX_CLK and
provides precise framing for data carried on E0_TCG[7:0] for the external
PMA. It is asserted when E0_TCG[7:0] contains valid data to be transmitted.
TBI mode: Transmit Code Group bit 8. Synchronous to GTX_CLK.
1
TO MII mode: Transmit Error. This signal is synchronous to E0_TX_CLK and
provides error indications.
G/MII mode: Transmit Error. This signal is synchronous to GTX_CLK and
provides error indications.
TBI mode: Transmit Code Group bit 9. Synchronous to GTX_CLK.
4
I
All modes: Receive Code Group Lower Nibble. This is a group of four signals,
sourced from an external PMA, that contains data aligned on nibble
boundaries and are driven synchronous to the E0_CLK. E0_RCG[3] is the
most significant bit and E0_RCG[0] is the least significant bit.
4
I
G/MII mode: Receive Code Group Upper Nibble This is a group of four signals,
sourced from an external PMA, that contains data aligned on byte boundaries and
are driven synchronous to the E0_CLK. E0_RCG[7] is most significant bit.
TBI mode: Receive Code Group Upper Nibble.
1
I
G/MII modes: Receive Data Valid. This indicates that the external PMA is
presenting recovered and decoded nibbles on the E0_RCG signals, and that
E0_CLK is synchronous to the recovered data in 100 Mb/s and 1000 Mb/s
operation. This signal encompasses the frame, starting with the
Start-of-Frame delimiter (JK) and excluding any End-of-Frame delimiter (TR).
TBI Mode: Transmit Code Group bit 8.
1
I
G/MII modes: Receive Error. This signal is synchronous to
E0_CLK/E0_PMA_CLK0 and provides media error indications.
TBI mode: Transmit Code Group bit 9.
1
I
G/MII modes: PHY Carrier Sense indication.
TBI mode: Indicates signals detected.
1
IO G/MII modes: PHY Collision Input.
TBI mode: Receive Byte Clock mode output. When low the E0_PMA_CLK0
and E0_PMA_CLK1 are active as half rate clocks. When high the
E0_PMA_CLK0 is active as a 125MHz clock input.
1
TO TBI mode: Enable Comma Detect. Enables SERDES to perform code group
alignment upon detection of comma.
1
TO TBI mode: Enable Wrap. Enables SERDES to loop transmit signals to receive
(Loopback).
1
TO TBI mode: PRBS Enable. Used to enable PRBS test mode inside TBI
SERDES devices.
1
I
TBI mode: PRBS Pass indicator input (high = pass).
22
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