GW80314GSSL7NK Datasheet, PDF (35/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Package Information
Table 19. Signal Pin Mode Behavior (Sheet 2 of 7)
Pin Name
Reset
Norm
SD_DQ[31:0]
Z*
VB
SD_DQS[17]
Z*
VB
SD_DQS/DM[16:9]
Z*
VB
SD_DQS[8]
Z*
VB
SD_DQS[7:0]
Z*
VB
SD_ECC
Z*
VB
SD_I2C_CLK
H
VO
SD_I2C_SDA
H
VB
SD_RAS#
1*
VO
SD_WE#
1*
VO
SD_PWRDELAY
VI
VI
E0_TCG[9:0]
VO
VO
E0_RCG[9:0]
VI
VI
E0_PCRS_SDET
VI
VI
E0_PCOL_RBCM
Z
VB
E0_ECMDT
Z
VO
E0_EWRAP
Z
VO
E0_PRBSEN
Z
VO
E0_PRBS_PASS
VI
VI
E0_RXCLK/E0_PMA_CLK0
VI
VI
E0_TXCLK/E0_PMA_CLK1
VI
VI
E1_TCG[9:0]
VO
VO
E1_RCG[9:0]
VI
VI
E1_PCRS_SDET
VI
VI
E1_PCOL_RBCM
Z
VB
E1_ECMDT
Z
VO
E1_EWRAP
Z
VO
E1_PRBSEN
Z
VO
E1_PRBS_PASS
VI
VI
E1_RXCLK/E1_PMA_CLK0
VI
VI
NOTES:
1. 1 = driven to V_CC
2. Z = output disabled (floats)
3. 0 = driven to V_SS
4. VB = acts like a valid bidirectional pin
5. ID = input is disabled
6. VO = a valid output level is driven
7. VO_M = a valid output level is driven (PCI Master)
8. VO_T = a valid output level is driven (PCI Target)
9. H = pulled up to V_CC
10.L = pulled down to V_SS
11. VI = need to drive a valid input level
12.VI_M = need to drive a valid input level (PCI Master)
13.VI_T = need to drive a valid input level (PCI Target)
14.PD = pull-up disabled
15.* = after power fail sequence completes
Hold
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
32-Bit PCI 32-Bit Mem
–
–
–
–
–
ID
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ECC Off
–
ID
–
ID
–
ID
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
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Datasheet
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