GW80314GSSL7NK Datasheet, PDF (15/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Features
2.5
DMA/XOR Engine
The DMA/XOR engine has four identical channels operating independently. Each channel can
function as a DMA engine or as an XOR engine. As a DMA engine, it can transfer data from any
port to any port and provide CRC calculation on the transferred data. As an XOR engine, it can
perform XOR operations on multiple blocks of data, memory fill operation, and parity checking
operation. For the DMA data transfer and XOR operation, a channel can be configured to operate
in Direct Mode (single operation) or Linked-List mode (multiple operations by stepping through a
linked series of Command Packets in external memory).
This DMA/XOR engine supports unaligned data transfers. The alignment or unalignment of data is
the responsibility of the DMA/XOR engine. The DMA/XOR registers specify the source,
destination, command packet address, mode of operation, the type of mapping to achieve the
proper byte alignment, and the byte count for a transaction. Note that the maximum byte count is
16 Mbytes. All DMA operations are assumed to be to prefetchable memory.
The DMA/XOR Engine has the following features:
• Four-channel support. Each channel operates independently.
• Data transfer to and from any port as a DMA engine
• XOR operation, memory fill, and parity checking as an XOR engine
• Scatter gather (or Linked-List) and direct modes
• XOR operation of up to 16 blocks of data
• Directly fill the store queue with the first block of XOR data (optional)
• Interrupt on completed segment, chain, and error
• Mode-selectable byte alignment on transferred data
• Calculate CRC on the DMA transferred data based on the CRC-32C algorithm required by the
iSCSI Specification
• Pipeline read requests or read and write requests for better performance
• Go/stop/halt control of data transfer operation
Datasheet
15