GW80314GSSL7NK Datasheet, PDF (24/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Package Information
Table 6.
GigE Signals (Sheet 3 of 3)
Pin Name
E1_RXCLK/
E1_PMA_CLK0
E1_TXCLK/
E1_PMA_CLK1
Management interface
MDC
MDIO
Gigabit Clocks
REF125M
GTX_CLK
GigE Pin Count
Count
1
1
Pin Type
Description
I
G/MII modes: Receive Clock from PMA.
TBI mode: PMA Receive Clock 0 or 125 MHz Receive Clock depending on
state of RBCMODE.
I
G/MII mode: 2.5 MHz or 25 MHz Transmit Clock.
TBI mode: PMA Receive Clock 1.
1
O Management Data Clock (2.5 MHz by 802.3 Specification.)
1
IO Management Data I/O Bidirectional Pin.
1
I
All Modes: 125 MHz reference clock input.
1
O All Modes: 125 MHz transmit clock output.
60
3.1.5
Peripheral Bus Interface Signals
This section describes signals for the GW80314 Peripheral Bus. Signals in this group are 3.3 V
LVTTL compatible.
Table 7.
Peripheral Bus Interface Signals
Pin Name
PBI_AD[31:0]
PBI_OE#
PBI_CS#[3:0]
PBI_LE
PBI_RDY#
PBI_RW
PBI Pin Count
Count
32
1
4
1
1
1
40
Pin Type
Description
IO Address/Data Bus.
O Output Enable.
O Chip Selects: Active low signal indicating that an external device has been
selected for access.
IO Latch Enable: Address latch signal to indicate when addresses are valid on
the PBI_AD bus.
I
Ready Input: In handshake mode, indicates that external device is ready to
commence transfer.
O Read/Write Enable: Low indicates a write access is underway.
24
Datasheet