GW80314GSSL7NK Datasheet, PDF (14/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Features
2.4
SDRAM Controller
The SDRAM Controller Core provides an interface to single and double data rate SDRAM. The
SDRAM Controller Core has the following features
• Synchronous SDRAM interface for PC100, PC200, and PC1600
• Two-port (64-bit data, 36-bit address) concurrent access to memory
• Internal arbiter with programmable priority for each port
• One-port (32-bit data, 18-bit address) access to registers
• Supports up to four physical (eight logical) banks
• Supports up to 32 bank interleaving (i.e., 32 pages open simultaneously)
• Flexible row and column address
• Optional ECC (single-bit error correction, multi-bit error detection)
• I/O interface compatible with DDR SDRAM
• I²C master only interface for DIMM detection
• Digital DLL for automatic DQS timing recovery
14
Datasheet