GW80314GSSL7NK Datasheet, PDF (77/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Electrical Specifications
4.4.7
Peripheral Bus Interface (PBI) Signal Timings
Table 38. PBI Interface Timing
Parameter
Timing Relationship
Min.
Max.
Units
Notes
t_SADLE Setup time from address valid to PBI_LE assertion
-6.0 + w
ns
1
t_HADLE Hold time from PBI_LE assertion to address release
7.5 + w
1, 2
t_SADCS Setup time from address valid to PBI_CS_B assertion
-7.5 + w
ns
1
t_DACSOE Delay time from PBI_CS_B assertion to PBI_OE_B assertion
-1.0 + w
2.5 + w
ns
1
t_DACSWE Delay time from PBI_CS_B assertion to PBI_RW assertion
0.0 + w 2.0 + w
ns
1
t_HWDCS Hold time from PBI_CS_B deassertion to data release for write
0.5
ns
data
t_DDCSWE Delay time from PBI_CS_B deassertion to PBI_RW
deassertion in handshaking mode
-2.0 + w 0.0 + w
ns
1
t_DHWECS Delay time from PBI_RW deassertion to PBI_CS_B
deassertion in non-handshaking mode
0.0 + w 2.0 + w
ns
1
t_DDCSOE Delay time from PBI_CS_B deassertion to PBI_OE_B
deassertion
-1.0
2.5
ns
t_VADRD Delay time from address valid to Read Data valid in latch mode
2.1 + w
ns
1, 3
t_WVRD Data valid window
3.7
ns
t_VADWD Write Data valid after address is released in latch mode
4.5
ns
t_VCSWD Write Data valid after PBI_CS_B assertion in non-latch mode
7.5
ns
NOTES:
1. Can be programmed to multiple integer SFN clock cycles. Assuming programmed to least amount of integer clock cycles.
Note that “+w” indicates programmable wait states.
2. Calculation includes one SFN clock cycle with a period of 7.5 ns.
3. Calculation includes two SFN clock cycles. SFN clock cycle period is 7.5 ns.
Datasheet
77