GW80314GSSL7NK Datasheet, PDF (69/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Electrical Specifications
4.2
Figure 5.
PLL Supply Pin Requirements
Package balls of the supply pins for the four Phase Lock Loops (PLLs) used on the GW80314
should be isolated and decoupled externally in order to provide the cleanest possible supply
environment. The following pins are used as PLL supplies in the GW80314: XS_PLL_AVCC,
SD_PLL_AVCC, P1_PLL_AVCC, and P2_PLL_AVCC. The recommended decoupling network
for these pins is shown in Figure 5.
In order to minimize the transient IR drops across the leads from the isolation network and the PLL
supply device pins, the trace routes must be kept short. It is preferred that the Cripple capacitor
used in Figure 5 be placed as close to the device pins as possible, on the backside of the board
underneath the device, when possible.
Intel^® GW80314 I/O Processor PLL Supply Decoupling Network
Note: The trace routing and
the RDC of the inductor
accounts for this resistance,
and should be in the range
shown
AVCC
Lfilter
470µH (Min)
4.7µH (Max)
(RF SMT)
Note: Lfilter must be
a high SRF SMT Wire
wound RF indicator
0.5Ω (Min)
4Ω (Max)
Ofilter
4.7µF (Min)
3.3µF (Max)
Note: The trace routing
resistance must be less than
0.1Ω to Cripple
Cripple
0.1µF
PLL_AVCC
DEVICE
PLL_AVSS
Note: Ofilter must be
a low ESR Tantalum
SMT capacitor
Note: The VCC to VSS 0.1 µF decoupling
cap needs to be as close to the device pins
as possible.
Capacitors should be Low ESR (High
Frequency) Ceramic chip capacitors
B1331-01
Datasheet
69