GW80314GSSL7NK Datasheet, PDF (10/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Introduction
ports can buffer incoming packets to allow for delayed access to the external bus. To limit the
latency and to provide a certain quality of service, the internal packets are limited to 256 bytes in
size. Larger PCI transactions are broken into 256-byte transactions at the PCI port.
1.1
Terminology
The following terms are used in this document.
Table 1.
Terms and Acronyms
Term/Acronym
Description
BAR
DMA
Embedded
G/MII
LVTTL
MAC
MIB
PCI
PCI/X
PCI-X
PHY
PMA
PMD
Primary
RMON
RX
Secondary
SNMP
STTL
TBI
Transparent
TX
VLAN
PCI-X Base Address Register
Direct Memory Address
Configuration causing the PCI-X block to provide BARs and address translation mechanism to PCI-X
Gigabit Media Independent Interface
Low-Voltage Transistor-Transistor Logic
Media Access Controller
Management Information Base
Transfers, interfaces or logic that are PCI Local Bus Specification, Revision 2.3 compatible
Used to signify either/or PCI or PCI-X designation.
Transfers, interfaces or logic that may be either PCI Local Bus Specification, Revision 2.3 or PCI-X Addendum
to the PCI Local Bus Specification, Revision 1.0a compatible
Physical connection device
Physical Media Attachment
Physical Media Device
A device with the PCI port attached to the processor bus side in a homogeneous, transparent system.
Remote Monitoring
Receiver
A device with the PCI port not attached to the host processor in a homogeneous, transparent system.
Simple Network Management Protocol
Schottky Transistor-Transistor Logic
Ten-Bit Interface
Configuration causing the PCI/X block to use base and limit registers for PCI-X side addressing.
Transmitter
Virtual Local Area Network
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Datasheet