GW80314GSSL7NK Datasheet, PDF (25/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Package Information
3.1.6
P1 PCI/X Signals
This section describes the GW80314 PCI/X signals on the P1 PCI/X bus.
Table 8.
P1 PCI/X Signals (Sheet 1 of 2)
Pin Name
P1_ACK64#
P1_AD[63:0]
P1_CBE#[7:0]
P1_CLK_IN
P1_CLK_OUT
P1_DEVSEL#
P1_FRAME#
P1_GNT#[1]
P1_GNT#[7:2]
P1_IDSEL
P1_INTA#
P1_INTB#
P1_INTC#
P1_INTD#
P1_IRDY#
P1_M66EN
P1_PAR
P1_PAR64
P1_PCIXCAP[1:0]
P1_PERR#
Count
1
64
8
1
1
1
1
1
6
1
1
1
1
1
1
1
1
1
2
1
Pin Type
IO
IO
IO
I
O
IO
IO
IO
TO
I
IO(OD)
IO(OD)
IO(OD)
IO(OD)
IO
I
IO
IO
I
IO
Description
Acknowledge 64-bit transaction: Active low signal asserted by a target to
indicate its willingness to participate in a 64-bit transaction. Driven by the
target; sampled by the master. Rescinded by the target at the end of the
transaction.
Address/Data Bus: Address and data are multiplexed over these pins
providing a 64-bit address/data bus.
Bus Command and Byte Enable Lines: Command and byte enable
information is multiplexed over all eight CBE lines.
PCI Input Clock: Clock In for the PCI/X Port 1 interface used to generate
fixed timing parameters. P1_CLK_IN can operate between 25 and
133 MHz
PCI Output Clock: Clock out for the PCI/X Port 1 interface. This is a valid
clock output only when this interface is used as the controlling resource.
Device Select: An active low indication from an agent that is the target of
the current transaction. Driven by the target; sampled by the master.
Rescinded by the target at the end of the transaction.
Cycle Frame for PCI/X Bus: An active low indication from the current bus
master of the beginning and end of a transaction. Driven by the bus master;
sampled by the selected target. Rescinded by the bus master at the end of
the transaction.
Grant: This is an input when an external arbiter is used and an output when
the internal arbiter is used. As an input it is used by the external arbiter to
grant the bus to the GW80314. As an output it is used by the internal arbiter
to grant the bus to an external master.
Grant: These are used by the internal arbiter to grant the bus to an external
master
Initialization Device Select: Used as a chip select during Configuration 0
read and write transactions
Interrupt A: An active low level sensitive indication of an interrupt.
Interrupt B: An active low level sensitive indication of an interrupt.
Interrupt C: An active low level sensitive indication of an interrupt.
Interrupt B: An active low level sensitive indication of an interrupt.
Initiator Ready: An active low indication of the current bus master’s ability
to complete the current data phase. Driven by the master; sampled by the
selected target.
PCI 66 MHz Enable: Controls the 33/66 MHz clock generation when in PCI
mode. When pulled low, it configures the PCI Port 1 PLL clock output for 33
MHz. When pulled high, it configures the PCI Port 1 PLL for 66 MHz
operation.
Parity: Carries even parity across P1_AD[31:0] and P1_C/BE[3:0]. Driven
by the master for the address and write data phases. Driven by the target
for read data phases.
Parity upper dword: Carries even parity across P1_AD[63:32] and
P1_CBE[7:4]. Driven by the master for address and write data phases.
Driven by the target for read data phases.
PCI/X Capability pin: Indicates the speed and mode of PCI/X interface
when configured as the control resource (P1_RSTDIR = 1).
Parity Error: An active low indication of a data parity error. Driven by the
target receiving data. Rescinded by that agent at the end of the transaction.
Datasheet
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