GW80314GSSL7NK Datasheet, PDF (13/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Features
2.3
CIU Interface
The Intel^® 80200 processor (80200) bus Core Interface Unit (CIU) provides a bridge between the
80200 bus and the Switch Fabric, an SDRAM controller, and 1 MB of on chip SRAM. It has a
queuing mechanism to store requests from up to two 80200s. The requests from a given 80200 are
completed on the 80200 bus in the order in which they are received. The CIU has the following
features:
• Up to two 80200 on the processor bus
• Up to four read or write requests from each processor
• Strict ordering rules for each processor
• Optional ECC for Processor Bus Data
• Up to four base address registers for the switch fabric
• Configurable software reset for the CIU and 80200 processors on startup
• Configurable with and without 1 Mbyte embedded SRAM
• Reset output for 80200 processors
• One base address register for the 1 MB on-chip SRAM
• Switch fabric access to SRAM
• 64-bit aligned data words
• 32-bit address decode
• 80200 external bus ECC protection
• Two-cycle wait states for write transactions to the SRAM from the processor bus
• Three-cycle wait states for read transactions to the SRAM from the processor bus
The CIU does not have the following features:
• Locked transactions
• Strict ordering rules between processors
Datasheet
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