GW80314GSSL7NK Datasheet, PDF (26/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Package Information
Table 8.
P1 PCI/X Signals (Sheet 2 of 2)
Pin Name
P1_PME#
P1_REQ#[1]
P1_REQ#[7:2]
P1_REQ64#
P1_RST#
P1_RSTDIR
P1_SERR#
P1_STOP#
P1_TRDY#
P1 PCI/X Pin Count
Count
1
1
6
1
1
1
1
1
1
110
Pin Type
IO(OD)
IO
I
IO
IO
I
OD
IO
IO
Description
Power Management (optional interrupt pin)
Bus Request: This is an output when an external arbiter is used and an
input when the internal arbiter is used. As an input it is used by an external
master to request the bus. As an output it is used by the GW80314 to
request the bus.
Bus Request: These signals are used by external masters to request the
PCI/X bus.
Request 64-bit transfer: An active low indication from the current master of
its choice to perform 64-bit transactions. Rescinded by the bus master at
the end of the transaction.
Reset: Asynchronous active low reset for PCI/X interface. When the
interface is the secondary side in a transparent bridge, this pin is
configured as an output.
Reset Direction:
0 = P1_RST# is input and P1_CLK_OUT is driven to 0.
1 = P1_RST# is output and P1_CLK_OUT is generated (PCI Port 1 is
controlling resource).
System Error: An active low indication of address parity error.
Stop: An active low indication from the target of its desire to stop the current
transition. Sampled by the master; rescinded by the target at the end of the
transaction
Target Ready: An active low indication of the current target’s ability to
complete the data phase. Driven by the target; sampled by the current bus
master. Rescinded by the target at the end of the transaction.
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Datasheet