GW80314GSSL7NK Datasheet, PDF (20/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Package Information
3.1.2
Intel XScale^® Microprocessor Bus Signals
This section describes the GW80314 Intel XScale^® microprocessor signals which are 3.3 V
LVTTL compatible.
Table 4.
Intel XScale^® Microprocessor Bus Signals
Pin Name
XS_A[15:0]
XS_ABORT
XS_BE[7:0]
XS_CLK
XS_CWF/
DBuswidth
XS_DQ[63:0]
XS_DVALID[1:0]
XS_HOLD[1:0]
XS_HLDA[1:0]¹
XS_ECC[7:0]
XS_FIQ[1]/PWRUP_SD_
BYP
(Configuration Pin)
XS_FIQ[0]
XS_IRQ[1]/
PWRUP_XS_BYP
(Configuration Pin)
XS_IRQ[0]/
PWRUP_FADJ
Configuration Pin
XS_LEN[2:0]
XS_RESET#
Intel XScale^®
microprocessor Pin Count
Count
16
1
8
1
1
64
2
2
2
8
1
1
1
1
3
1
113
Pin Type
Description
I
Address: During the first cycle of the issue phase, it carries the upper 16 bits
of the address for the access. During the second cycle of the issues phase, it
carries the lower 16 bits of the address.
O Transaction Abort: Indicates the next transaction on the data bus is aborted.
IO Processor Bus Byte Enables.
IO Intel XScale^® microprocessor bus clock: Output clock for Intel XScale^®
microprocessor interface and SDRAM controller. This pin acts as an input in
Scan Mode.
O Critical word first: Indicates the order in which the current 32-byte read burst is
returning. Also when the Intel XScale^® microprocessor bus is in reset this
signal is driven low to indicated data bus width is 64-bit.
IO Data bus.
O
Data Valid: One for each Intel XScale^® microprocessor on the bus. When
asserted high, it indicates that two cycles later, data is valid on XS_DQ,
XS_BE, and XS_ECC.
O
Signal to Intel XScale^® microprocessor to request Intel XScale^®
microprocessor to release the Intel XScale^® microprocessor bus.
I
Signal from Intel XScale^® microprocessor to acknowledge the release of the
Intel XScale^® microprocessor bus in response to the assertion of the
corresponding XS_HOLD signal.
IO Data Check Bits for Intel XScale^® microprocessor ECC Bus Protect.
IO Interrupt: indicates a fast interrupt to processor 1. During power-up, this pin is
latched at the rising edge of reset and used to enable the SDRAM PLL bypass
mode when latched high.
O Interrupt: indicates a fast interrupt to processor 0.
IO Interrupt: indicates a interrupt to processor 1. During power-up, this pin is
latched at the rising edge of reset and is used to enable the Intel XScale^®
microprocessor PLL bypass mode when latched high.
IO Interrupt: indicates a interrupt to processor 0. During power-up, this pin is
used to program Intel XScale^® microprocessor PLL frequency adjust logic.
• PWRUP_FADJ = 0, Intel XScale^® PLL Frequency = 3/4 * SFN_CLK.
• PWRUP_FADJ = 1, Intel XScale^® PLL Frequency = SFN_CLK.
I
Control and length access:
During the first cycle of the issue phase:
• XS_LEN[2] (ADS#) the start of a bus request.
• XS_LEN[0] (W/R#) indicates whether the current request is a read
(XS_LEN[0] = 0) or a write (XS_LEN[0] =1).
During the second cycle of the issue phase:
• XS_LEN[2:0] indicates the length of the request.
O
Reset pin: When output is low the Intel XScale^® microprocessor bus is reset
and Intel XScale^® microprocessor interface is in reset.
NOTES:
1. For single processor configuration, XS_HLDA[0] should be tied low and XS_HLDA[1] should be tied high.
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Datasheet