GW80314GSSL7NK Datasheet, PDF (17/88 Pages) Intel Corporation – Intel® GW80314 I/O Companion Chip

Intel® GW80314 I/O Companion Chip
Features
2.7
Interrupt Controller
The interrupt controller is a programmable, register based, and multiple port design that meets
OpenPIC Specification, Revision 1.2.
The interrupt controller has the following features:
• Support for two Intel^® 80200 processors
• Sixteen interrupt priority levels (0 to 15)
• Level/edge sensibility programmable for 24 IRQ inputs
• Level/edge sensibility programmable for four output pins
• Up to 24 input interrupt pins
• Up to four output interrupt pins
• Four doorbell registers for additional interrupts
• Four general-purpose mailbox registers
• Four global precision timers
• All registers are read/write 32 bits based
• Multiple delivery modes are supported:
— Directed-single destination
— Directed-multicast
— Distributed-multiple destination
• Nesting of interrupt events
• Spurious vector generation capable
• Soft set override for all input sources (maximum 24)
• Processor initialization registers
• All registers are at “Known Reset State” on power-up
Datasheet
17