82433LX Datasheet, PDF (9/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
2 1 Host Interface Signals
Signal Type
Description
A 15 0 t s
ADDRESS BUS The bi-directional A 15 0 lines are connected to the address lines of the
host bus The high order LBX (determined at reset time using the EOL signal) is
connected to A 31 16 and the low order LBX is connected to A 15 0 The host address
bus is common with the Pentium processor second level cache PCMC and the two
LBXs During CPU cycles A 31 3 are driven by the CPU and A 2 0 are driven by the
PCMC all are inputs to the LBXs During inquire cycles the LBX drives the PCI master
address onto the host address lines A 31 0 This snoop address is driven to the CPU and
the PCMC by the LBXs to snoop L1 and the integrated second level tags respectively
During PCI configuration cycles bound for the PCMC the LBXs will send or receive the
configuration data to from the PCMC by copying the host data bus to from the host
address bus The LBX drives both halves of the Qword host data bus with data from the
32-bit address during PCMC configuration read cycles The LBX drives the 32-bit address
with either the low Dword or the high Dword during PCMC configuration write cycles
In the 82433NX these pins contain weak internal pull-down resistors
The high order 82433NX LBX samples A11 at the falling edge of reset to configure the
LBX for PLL test mode When A11 is sampled low the LBX is in normal operating mode
When A11 is sampled high the LBX drives the internal HCLK from the PLL on the EOL
pin Note that A11 on the high order LBX is connected to the A27 line on the CPU address
bus This same address line is used to put the PCMC into PLL test mode
D 31 0 t s
HOST DATA The bi-directional D 31 0 lines are connected to the data lines of the host
data bus The high order LBX (determined at reset time using the EOL signal) is
connected to the host data bus D 63 48 and D 31 16 lines and the low order LBX is
connected to the host data bus D 47 32 and D 15 0 lines In the 82433LX these pins
contain weak internal pull-up resistors
In the 82433NX these pins contain weak internal pull-down resistors
HP 3 0 t s
HOST DATA PARITY HP 3 0 are the bi-directional byte parity signals for the host data
bus The low order parity bit HP 0 corresponds to D 7 0 while the high order parity bit
HP 3 corresponds to D 31 24 The HP 3 0 signals function as parity inputs during write
cycles and as parity outputs during read cycles Even parity is supported and the HP 3 0
signals follow the same timings as D 31 0 In the 82433LX these pins contain weak
internal pull-up resistors
In the 82433NX these pins contain weak internal pull-down resistors
9