82433LX Datasheet, PDF (14/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
3 1 5 CPU-TO-PCI READ PREFETCH BUFFER
This prefetch buffer is organized as a single buffer
4 Dwords deep The buffer is organized as a simple
FIFO reads from the buffer are sequential the buff-
er does not support random access of its contents
To support reads of less than a Dword the FIFO
read pointer can function with or without a pre-incre-
ment The pointer can also be reset to the first entry
before a Dword is driven When a Dword is read it is
driven onto both halves of the host data bus
Commands driven on the HIG 4 0 lines enable read
addresses to be sent onto PCI the addresses are
driven using PIG 3 0 commands Read data is
latched into the LBX by commands driven on the
PIG 3 0 lines and the data is driven onto the host
data bus using commands driven on the HIG 4 0
lines
The LBX calculates Dword parity on PCI read data
sending the proper value to the PCMC on PPOUT
The LBX does not generate byte parity on the host
data bus when the CPU reads PCI
3 2 LBX Interface Command
Descriptions
This section describes the functionality of the HIG
MIG and PIG commands driven by the PCMC to the
LBXs
3 2 1 HOST INTERFACE GROUP HIG 4 0
The Host Interface commands are shown in Table 1
These commands are issued by the host interface of
the PCMC to the LBXs in order to perform the fol-
lowing functions
 Reads from CPU-to-PCI read prefetch buffer
when the CPU reads from PCI
 Stores write-back data to PCI-to-memory read
prefetch buffer when PCI read address results in
a hit to a modified line in first or second level
caches
 Posts data to CPU-to-memory write buffer in the
case of a CPU to memory write
 Posts data to CPU-to-PCI write buffer in the case
of a CPU to PCI write
 Drives host address to Data lines and data to ad-
dress lines for programming the PCMC configura-
tion registers
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