82433LX Datasheet, PDF (28/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
A similar sequence is defined for PCI master reads
While it is possible to know when to stop driving read
data due to the fact that the read address is latched
into the PCMC before any read data is driven on PCI
the use of the EOL signal for PCI master reads sim-
plifies the logic internal to the PCMC Figure 10 illus-
trates the timing of EOL with respect to the PIG 3 0
commands to drive out PCI read data
Note that unlike the PCI master write sequence the
STOP signal is asserted with the last data transfer
not after
1 The LPMA command sampled at the end of the
second clock causes the EOL signal to assert if
there is only one Dword left in the line otherwise
it will be negated The first TRDY will also be
the last and the STOP signal will be asserted
with TRDY
2 The SPMRH command causes the count of the
number of Dwords left in the line to be decre-
mented If this count reaches one the EOL signal
is asserted The next TRDY will be the last and
STOP is asserted with TRDY
Figure 10 EOL Signal Timing for PCI Master Reads
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