82433LX Datasheet, PDF (21/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
3 3 LBX Timing Diagrams
This section describes the timing relationship be-
tween the LBX control signals and the interface
buses
3 3 1 HIG 4 0 COMMAND TIMING
The commands driven on HIG 4 0 can cause the
host address bus and or the host data bus to be
driven and latched The following timing diagram il-
lustrates the timing relationship between the driven
command and the buses The ‘‘host bus’’ in Figure 4
could be address and or data
Note that the Drive command takes two cycles to
drive the host data bus but only one to drive the
address When the NOPC command is sampled the
LBX takes only one cycle to release the host bus
The Drive commands in Figure 4 are any of the
following
CMR
CPRF
CPRA
CPRB
CPRQ
DPRA
DPWA ADCPY
DACPYH DACPYL DRVFF
The Latch command in Figure 4 is any of the
following
SWB0
SWB1
SWB2
SWB3
PCMWQ PCMWFQ PCMWNQ PCPWL
MCP3L MCP2L
MCP1L
PCPWH
MCP3H MCP2H
LCPRAD PSCD
Figure 4 HIG 4 0 Command Timing
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