82433LX Datasheet, PDF (20/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
PPMWA
PPMWD
SPMRH
SPMRL
SPMRN
LCPRF
LCPRA
This command selects a new buffer
and places the PCI master address
latch value into the address register
for that buffer The next PPMWD
command posts write data in the first
location of this newly selected buff-
er This command also causes the
EOL logic to decrement the count of
Dwords remaining in the line
This command stores the value in
the AD latch into the next data loca-
tion in the currently selected buffer
This command also causes the EOL
logic to decrement the count of
Dwords remaining in the line
This command sends the high order
Dword from the first Qword of the
PCI-to-Memory Read Buffer onto
PCI This command also causes the
EOL logic to decrement the count of
Dwords remaining in the line
This command sends the low order
Dword from the first Qword of the
PCI-to-Memory Read Buffer onto
PCI This command also selects the
Dword alignment for the transaction
and causes the EOL logic to decre-
ment the count of Dwords remaining
in the line
This command sends the next
Dword from the PCI-to-Memory
Read Buffer onto PCI This com-
mand also causes the EOL logic to
decrement the count of Dwords re-
maining in the line This command is
used for the second and all subse-
quent Dwords of the current transac-
tion
This command acquires the value of
the AD 31 0 lines into the first loca-
tion in the CPU-to-PCI Read Pre-
fetch Buffer until a different com-
mand is driven
When driven after a LCPRF or
LCPRB command this command
latches the value of the AD 31 0
lines into the next location into the
CPU-to-PCI Read Prefetch Buffer
When driven after another LCPRA
command this command latches
the value on AD 31 0 into the same
location in the CPU-to-PCI Read
Prefetch Buffer overwriting the pre-
vious value
LCPRB
DCPWA
DCPWD
DCPWL
DCCPD
BCPWR
SCPA
LPMA
When driven after a LCPRA com-
mand this command latches the val-
ue of the AD 31 0 lines into the next
location into the CPU-to-PCI Read
Prefetch Buffer When driven after
another LCPRB command this com-
mand latches the value on AD 31 0
into the same location in the CPU-to-
PCI Read Prefetch Buffer overwrit-
ing the previous value
This command drives the next ad-
dress in the CPU-to-PCI Write Buffer
onto PCI The read pointer of the
FIFO is not incremented
This command drives the next data
Dword in the CPU-to-PCI Write Buff-
er onto PCI The read pointer of the
FIFO is incremented on the next
PCLK if TRDY is asserted
This command drives the previous
data Dword in the CPU-to-PCI Write
Buffer onto PCI This is the data
which was driven by the last DCPWD
command The read pointer of the
FIFO is not incremented
This command discards the current
Dword in the CPU-to-PCI Write Buff-
er This is used to clear write data
when the write transaction termi-
nates with master abort where
TRDY is never asserted
For this command the CPU-to-PCI
Write Buffer is ‘‘backed up’’ one en-
try such that the address data pair
last driven with the DCPWA and
DCPWD commands will be driven
again on the AD 31 0 lines when
the commands are driven again
This command is used when the tar-
get has retried the write cycle
This command drives the value on
the host address bus onto PCI
This command stores the previous
AD 31 0 value into the PCI master
address latch If the EOL logic deter-
mines that the requested Dword is
the last Dword of a line then the
EOL signal will be asserted other-
wise the EOL signal will be negated
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