82433LX Datasheet, PDF (10/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
2 2 Main Memory (Dram) Interface Signals
Signal Type
Description
MD 31 0 t s
MEMORY DATA BUS MD 31 0 are the bi-directional data lines for the memory data
bus The high order LBX (determined at reset time using the EOL signal) is connected to
the memory data bus MD 63 48 and MD 31 16 lines and the low order LBX is
connected to the memory data bus MD 47 32 and MD 15 0 lines The MD 31 0
signals drive data destined for either the host data bus or the PCI bus The MD 31 0
signals input data that originated from either the host data bus or the PCI bus These
pins contain weak internal pull-up resistors
MP 3 0 t s MEMORY PARITY MP 3 0 are the bi-directional byte enable parity signals for the
memory data bus The low order parity bit MP 0 corresponds to MD 7 0 while the high
order parity bit MP 3 corresponds to MD 31 24 The MP 3 0 signals are parity outputs
during write cycles to memory and parity inputs during read cycles from memory Even
parity is supported and the MP 3 0 signals follow the same timings as MD 31 0 These
pins contain weak internal pull-up resistors
2 3 PCI Interface Signals
Signal Type
Description
AD 15 0 t s
ADDRESS AND DATA AD 15 0 are bi-directional data lines for the PCI bus The
AD 15 0 signals sample or drive the address and data on the PCI bus The high order
LBX (determined at reset time using the EOL signal) is connected to the PCI bus
AD 31 16 lines and the low order LBX is connected to the PCI AD 15 0 lines
TRDY in
TARGET READY TRDY indicates the selected (targeted) device’s ability to complete
the current data phase of the bus operation For normal operation TRDY is tied
asserted low When the TRDY option is enabled in the PCMC (for zero wait-state PCI
burst writes) TRDY should be connected to the PCI bus
2 4 PCMC Interface Signals
Signal Type
Description
HIG 4 0 in
HOST INTERFACE GROUP These signals are driven from the PCMC and control the
host interface of the LBX The 82433LX decodes the binary pattern of these lines to
perform 29 unique functions (30 for the 83433NX) These signals are synchronous to the
rising edge of HCLK
MIG 2 0 in
MEMORY INTERFACE GROUP These signals are driven from the PCMC and control
the memory interface of the LBX The LBX decodes the binary pattern of these lines to
perform 7 unique functions These signals are synchronous to the rising edge of HCLK
PIG 3 0 in
PCI INTERFACE GROUP These signals are driven from the PCMC and control the PCI
interface of the LBX The LBX decodes the binary pattern of these lines to perform 15
unique functions These signals are synchronous to the rising edge of HCLK
MDLE in
MEMORY DATA LATCH ENABLE During CPU reads from DRAM the LBX uses a
clocked register to transfer data from the MD 31 0 and MP 3 0 lines to the D 31 0 and
HP 3 0 lines MDLE is the clock enable for this register Data is clocked into this register
when MDLE is asserted The register retains its current value when MDLE is negated
During CPU reads from main memory the LBX tri-states the D 31 0 and HP 3 0 lines
on the rising edge of MDLE when HIG 4 0 ^eNOPC
DRVPCI in
DRIVE PCI BUS This signals enables the LBX to drive either address or data
information onto the PCI AD 15 0 lines
10