82433LX Datasheet, PDF (17/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
PCPWL
MCP3L
MCP2L
MCP1L
PCPWH
MCP3H
MCP2H
MCP1H
LCPRAD
This command posts the low Dword of
a CPU-to-PCI write The CPU-to-PCI
Write Buffer stores a Dword of PCI ad-
dress for every Dword of data Hence
this command also stores the address
of the Low Dword in the address loca-
tion for the data Address bit 2 (A2) is
not stored directly This command as-
sumes a value of 0 for A2 and this is
what is stored
This command merges the 3 most sig-
nificant bytes of the low Dword of the
host data bus into the last Dword post-
ed to the CPU-to-PCI write buffer The
address is not modified
This command merges the 2 most sig-
nificant bytes of the low Dword of the
host data bus into the last Dword post-
ed to the CPU-to-PCI write buffer The
address is not modified
This command merges the most signif-
icant byte of the low Dword of the host
data bus into the last Dword posted to
the CPU-to-PCI write buffer The ad-
dress is not modified
This command posts the upper Dword
of a CPU-to-PCI write with its address
into the address location Hence to do
a Qword write PCPWL has to be fol-
lowed by a PCPWH Address bit 2 (A2)
is not stored directly This command
forces a value of 1 for A2 and this is
what is stored
This command merges the 3 most sig-
nificant bytes of the high Dword of the
host data bus into the last Dword post-
ed to the CPU-to-PCI Write Buffer The
address is not modified
This command merges the 2 most sig-
nificant bytes of the high Dword of the
host data bus into the last Dword post-
ed to the CPU-to-PCI Write Buffer The
address is not modified
This command merges the most signif-
icant byte of the high Dword of the host
data bus into the last Dword posted to
the CPU-to-PCI Write Buffer The ad-
dress is not modified
This command latches the host ad-
dress to drive on PCI for a CPU-to-PCI
read It is necessary to latch the ad-
dress in order to drive inquire address-
es on the host address bus before the
CPU address is driven onto PCI
DPRA
DPWA
ADCPY
DACPYH
DACPYL
PSCD
DRVFF
PCPWHC
The PCI memory read address is
latched in the PCI A D latch by a PIG
command LCPRAD this address is
driven onto the host address bus by
DPRA Used in PCI to memory read
transaction
The DPWA command drives the ad-
dress of the current PCI Master Write
Buffer onto the host address bus This
command is potentially driven for multi-
ple cycles When it is no longer driven
the read pointer will increment to point
to the next buffer and a subsequent
DPWA command will read the address
from that buffer
This command drives the host data
bus with the host address The ad-
dress is copied on the high and low
halves of the Qword data bus i e
A 31 0 is copied onto D 31 0 and
D 63 32 This command is used when
the CPU writes to the PCMC configura-
tion registers
This command drives the host address
bus with the high Dword of host data
This command is used when the CPU
writes to the PCMC configuration regis-
ters
This command drives the host address
bus with the low Dword of host data
This command is used when the CPU
writes to the PCMC configuration regis-
ters
This command is used to post the val-
ue of the Special Cycle code into the
CPU-to-PCI Posted Write Buffer The
value is driven onto the A 31 0 lines
by the PCMC after acquiring the ad-
dress bus by asserting AHOLD The
value on the A 31 0 lines is posted
into the DATA location in the CPU-to-
PCI Posted Write Buffer
This command causes the LBX to drive
all ‘‘1s’’ (i e FFFFFFFFh) onto the host
data bus It is used for CPU reads from
PCI that terminate with master abort
This command posts the high half of
the CPU data bus The LBXs post the
high half of the data bus even if A2
from the PCMC is low This command
is used during configuration writes
when using PCI configuration access
mechanism 1
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