82433LX Datasheet, PDF (12/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
3 0 FUNCTIONAL DESCRIPTION
3 1 LBX Post and Prefetch Buffers
This section describes the five write posting and
read prefetching buffers implemented in the LBX
The discussion in this section refers to the operation
of both LBXs in the system
3 1 1 CPU-TO-MEMORY POSTED WRITE
BUFFER
The write buffer is a queue 4 Qwords deep it loads
Qwords from the CPU and stores Qwords to memo-
ry It is 4 Qwords deep to accommodate write-backs
from the first or second level cache It is organized
as a simple FIFO Commands driven on the HIG 4 0
lines store Qwords into the buffer while commands
on the MIG 2 0 lines retire Qwords from the buffer
While retiring Qwords to memory the DRAM control-
ler unit of the PCMC will assert the appropriate MA
CAS 7 0 and WE signals The PCMC keeps
track of full empty states status of the data and
address
Byte parity for data to be written to memory is either
propagated from the host bus or generated by the
LBX The LBX generates parity for data from the
second level cache when the second level cache
does not implement parity
3 1 2 PCI-TO-MEMORY POSTED WRITE BUFFER
The buffer is organized as 2 buffers (4 Dwords
each) There is an address storage register for each
buffer When an address is stored one of the two
buffers is allocated and subsequent Dwords of data
are stored beginning at the first location in that buff-
er Buffers are retired to memory strictly in order
Qword at a time
Commands driven on the PIG 3 0 lines post ad-
dresses and data into the buffer Commands driven
on HIG 4 0 result in addresses being driven on the
host address bus Commands driven on MIG 2 0
result in data being retired to DRAM
For cases where the address targeted by the first
Dword is odd i e A 2 ^e1 and the data is stored in
an even location in the buffer the LBX correctly
aligns the Dword when retiring the data to DRAM In
other words the buffer is capable of retiring a Qword
to memory where the data in the buffer is shifted by
1 Dword (Dword is position 0 shifted to 1 1 shifted
to 2 etc ) The DRAM controller of the PCMC asserts
the correct CAS 7 0 signals depending on the PCI
C BE 3 0 signals stored in the PCMC for that
Dword
The End Of Line (EOL) signal is used to prevent PCI
master writes from bursting past the cache line
boundary The device that provides ‘‘warning’’ to the
PCMC is the low order LBX This device contains the
PCI master write low order address bits necessary to
determine how many Dwords are left to the end of
the line Consequently the LBX protocol uses the
EOL signal from the low order LBX to provide this
‘‘end-of-line’’ warning to the PCMC so that it may
retry a PCI master write when it bursts past the
cache line boundary This protocol is described fully
in Section 3 3 6
The LBX calculates Dword parity on PCI write data
sending the proper value to the PCMC on PPOUT
The LBX generates byte parity on the MP signals for
writing into DRAM
3 1 3 PCI-TO-MEMORY READ PREFETCH
BUFFER
This buffer is organized as a line buffer (4 Qwords)
for burst transfers to PCI The data is transferred into
the buffer a Qword at a time and read out a Dword at
a time The LBX then effectively decouples the
memory read rate from the PCI rate to increase con-
currence
Each new transaction begins by storing the first
Dword in the first location in the buffer The starting
Dword for reading data out of the buffer onto PCI
must be specified within a Qword boundary that is
the first requested Dword on PCI could be an even
or odd Dword If the snoop for a PCI master read
results in a write-back from first or second level
caches this write back is sent directly to PCI and
main memory The following two paragraphs de-
scribe this process for cache line write-backs
Since the write-back data from L1 is in linear order
writing into the buffer is straightforward Only those
Qwords to be transferred into PCI are latched into
the PCI-to-memory read buffer For example if the
address targeted by PCI is in the 3rd or 4th Qword in
the line the first 2 Qwords of write back data are
discarded and not written into the read buffer The
primary cache write-back must always be written
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