82433LX Datasheet, PDF (39/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
4 4 6 ADDRESS DATA TRDY EOL TEST TSCON AND PARITY TIMING 60 MHz (82433LX)
Functional Operating Range V_CC ^e 4 75V to 5 25V T_CASE ^e 0 C to ^a85 C
Symbol
Parameter
Min Max Figure Notes
t20a
AD 15 0 Output Enable Delay from PCLK Rising
2
17
t20b
AD 15 0 Valid Delay from PCLK Rising
2
11
14
1
t20c
AD 15 0 Setup Time to PCLK Rising
7
15
t20d
AD 15 0 Hold Time from PCLK Rising
0
15
t20e
AD 15 0 Float Delay from DRVPCI Falling
2
10
16
t21a
TRDY Setup Time to PCLK Rising
7
15
t21b
TRDY Hold Time from PCLK Rising
0
15
t22a
D 31 0 HP 3 0 Output Enable Delay from HCLK Rising 0
7 9 17
2
t22b
D 31 0 HP 3 0 Float Delay from HCLK Rising
3 1 15 5 16
t22c
D 31 0 HP 3 0 Float Delay from MDLE Rising
2
11 0 16
3
t22d
D 31 0 HP 3 0 Valid Delay from HCLK Rising
0
7 8 14
2
t22e
D 31 0 HP 3 0 Setup Time to HCLK Rising
34
15
t22f
D 31 0 HP 3 0 Hold Time from HCLK Rising
03
15
t23a
HA 15 0 Output Enable Delay from HCLK Rising
0
15 2 17
t23b
HA 15 0 Float Delay from HCLK Rising
0
15 2 16
t23c
HA 15 0 Valid Delay from HCLK Rising
0
18 5 14
7
t23cc
HA 15 0 Valid Delay from HCLK Rising
0
15 5
8
t23d
HA 15 0 Setup Time to HCLK Rising
15 0
15
4
t23e
HA 15 0 Setup Time to HCLK Rising
41
15
5
t23f
HA 15 0 Hold Time from HCLK Rising
03
15
t24a
MD 31 0 MP 3 0 Valid Delay from HCLK Rising
0
12 0 14
6
t24b
MD 31 0 MP 3 0 Setup Time to HCLK Rising
44
15
t24c
MD 31 0 MP 3 0 Hold Time from HCLK Rising
10
15
t25
EOL PPOUT Valid Delay from PCLK Rising
2 3 17 2 14
2
t26a
All Outputs Float Delay from TSCON Falling
0
30
16
t26b
All Outputs Enable Delay from TSCON Rising
0
30
17
NOTES
1 Min 0 pF Max 50 pF
2 0 pF
3 When NOPC command sampled on previous rising HCLK on HIG 4 0
4 CPU to PCI Transfers
5 When ADCPY command is sampled on HIG 4 0
6 50 pF
7 When DACPYL or DACPYH commands are sampled on HIG 4 0
8 Inquire cycle
39