82433LX Datasheet, PDF (27/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
3 3 6 PIG 3 0 END-OF-LINE
WARNING SIGNALS EOL
When posting PCI master writes the PCMC must be
informed when the line boundary is about to be over-
run as it has no way of determining this itself (recall
that the PCMC does not receive any address bits
from PCI) The low order LBX determines this as it
contains the low order bits of the PCI master write
address and also tracks how many Dwords of write
data have been posted Therefore the low order
LBX component sends the ‘‘end-of-line’’ warning to
the PCMC This is accomplished with the EOL signal
driven from the low order LBX to the PCMC Figure 9
illustrates the timing of this signal
1 The FRAME signal is sampled asserted in the
first cycle The LPMA command is driven on the
PIG 3 0 signals to hold the address while it is
being decoded (e g in the MEMCS decode cir-
cuit of the 82378 SIO) The first data (D0) remains
on the bus until TRDY is asserted in response
to MEMCS being sampled asserted in the third
clock
2 The PPMWA command is driven in response to
sampling MEMCS asserted TRDY is asserted
in this cycle indicating that D0 has been latched at
the end of the fourth clock The action of the
PPMWA command is to transfer the PCI address
captured in the PCI AD latch at the end of the first
clock to the posting buffer and open the PCI AD
latch in order to capture the data This data will be
posted to the write buffer in the following cycle by
the PPMWD command
3 The EOL signal is first negated when the LPMA
command is driven on the PIG 3 0 signals How-
ever if the first data Dword accepted is also the
last that should be accepted the EOL signal will
be asserted in the third clock This is the ‘‘end-of-
line’’ indication In this case the EOL signal is as-
serted as soon as the LPMA command has been
latched The action by the PCMC in response is to
negate TRDY and assert STOP in the fifth
clock Note that the EOL signal is asserted even
before the MEMCS signal is sampled asserted
in this case The EOL signal will remain asserted
until the next time the LPMA command is driven
4 If the second Dword is the last that should be
accepted the EOL signal will be asserted in the
fifth clock to negate TRDY and assert STOP
on the following clock The EOL signal is asserted
in response to the PPMWA command being sam-
pled and relies on the knowledge that TRDY for
the first Dword of data will be sampled asserted
by the master in the same cycle (at the end of the
fourth clock) Therefore to prevent a third asser-
tion of TRDY in the sixth clock the EOL signal
must be asserted in the fifth clock
Figure 9 EOL Signal Timing for PCI Master Writes
290478 – 10
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