82433LX Datasheet, PDF (15/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
Table 1 HIG Commands
Command Code
Description
NOPC
00000b No Operation on CPU Bus
CMR
11100b CPU Memory Read
CPRF
00100b CPU Read First Dword from CPU-to-PCI Read Prefetch Buffer
CPRA
00101b CPU Read Next Dword from CPU-to-PCI Read Prefetch Buffer Toggle A
CPRB
00110b CPU Read Next Dword from CPU-to-PCI Read Prefetch Buffer Toggle B
CPRQ
00111b CPU Read Qword from CPU-to-PCI Read Prefetch Buffer
SWB0
01000b Store Write-Back Data Qword 0 to PCI-to-Memory Read Buffer
SWB1
01001b Store Write-Back Data Qword 1 to PCI-to-Memory Read Buffer
SWB2
01010b Store Write-Back Data Qword 2 to PCI-to-Memory Read Buffer
SWB3
01011b Store Write-Back Data Qword 3 to PCI-to-Memory Read Buffer
PCMWQ 01100b Post to CPU-to-Memory Write Buffer Qword
PCMWFQ 01101b Post to CPU-to-Memory Write and PCI-to-Memory Read Buffer First Qword
PCMWNQ 01110b Post to CPU-to-Memory Write and PCI-to-Memory Read Buffer Next Qword
PCPWL 10000b Post to CPU-to-PCI Write Low Dword
MCP3L
10011b Merge to CPU-to-PCI Write Low Dword 3 Bytes
MCP2L
10010b Merge to CPU-to-PCI Write Low Dword 2 Bytes
MCP1L
10001b Merge to CPU-to-PCI Write Low Dword 1 Byte
PCPWH 10100b Post to CPU-to-PCI Write High Dword
MCP3H 10111b Merge to CPU-to-PCI Write High Dword 3 Bytes
MCP2H 10110b Merge to CPU-to-PCI Write High Dword 2 Bytes
MCP1H 10101b Merge to CPU-to-PCI Write High Dword 1 Byte
LCPRAD 00001b Latch CPU-to-PCI Read Address
DPRA
11000b Drive Address from PCI A D Latch to CPU Address Bus
DPWA
11001b Drive Address from PCI-to-Memory Write Buffer to CPU Address Bus
ADCPY
11101b Address to Data Copy in the LBX
DACPYH 11011b Data to Address Copy in the LBX High Dword
DACPYL 11010b Data to Address Copy in the LBX Low Dword
PSCD
01111b Post Special Cycle Data
DRVFF
11110b Drive FF FF (All 1’s) onto the Host Data Bus
PCPWHC 00011b Post to CPU-to-PCI Write High Dword Configuration
NOTE
All other patterns are reserved
15