82433LX Datasheet, PDF (42/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
Symbol
t23a
t23b
t23c
t23cc
t23d
t23e
t23f
t24a
t24b
t24c
t25
t26a
t26b
Functional Operating Range V_CC ^e 4 75V to 5V V_CC3 ^e 3 135V to 3 465V
T_CASE ^e 0 C to ^a85 C (Continued)
Parameter
Min Max Figure
HA 15 0 Output Enable Delay from HCLK Rising 0
13 5 17
HA 15 0 Float Delay from HCLK Rising
0
13 5 16
HA 15 0 Valid Delay from HCLK Rising
0
17 5 14
HA 15 0 Valid Delay from HCLK Rising
0
13 5
HA 15 0 Setup Time to HCLK Rising
15
15
HA 15 0 Setup Time to HCLK Rising
42
15
HA 15 0 Hold Time from HCLK Rising
03
15
MD 31 0 MP 3 0 Valid Delay from HCLK Rising 0
12 0 14
MD 31 0 MP 3 0 Setup Time to HCLK Rising
44
15
MD 31 0 MP 3 0 Hold Time from HCLK Rising
10
15
EOL PPOUT Valid Delay from PCLK Rising
23
17 2 14
All Outputs Float Delay from TSCON Falling
0
30
16
All Outputs Enable Delay from TSCON Rising
0
30
17
NOTE
1 Min 0 pF Max 50 pF
2 0 pF
3 When NOPC command sampled on previous rising HCLK on HIG 4 0
4 CPU to PCI Transfers
5 When ADCPY command is sampled on HIG 4 0
6 50 pF
7 When DACPYL or DACPYH commands are sampled on HIG 4 0
8 Inquire cycle
Notes
7
8
4
5
6
2
4 5 4 TEST TIMING (82433NX)
Functional Operating Range V_CC ^e 4 75V to 5 25V V_CC3 ^e 3 135V to 3 465V T_CASE ^e 0 C to ^a85 C
Symbol
Parameter
Min Max Figure
Notes
t30
All Test Signals Setup Time to HCLK
10 0
PCLK Rising
In PLL Bypass Mode
t31
All Test Signals Hold Time to HCLK
12 0
PCLK Rising
In PLL Bypass Mode
t32
Test Setup Time to HCLK PCLK Rising 15 0
15
t33
Test Hold Time to HCLK PCLK Rising 5 0
15
t34
PPOUT Valid Delay from PCLK Rising
00
500 15
In PLL Bypass Mode
42