82433LX Datasheet, PDF (25/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
3 3 5 PIG 3 0 READ PREFETCH BUFFER
COMMAND TIMING
The structure of the CPU-to-PCI read prefetch buffer
requires special considerations due to the partition
of the PCMC and LBX The PCMC interfaces only to
the PCI control signals while the LBXs interface only
to the data Therefore it is not possible to latch a
Dword of data into the prefetch buffer after it is quali-
fied by TRDY Instead the data is repetitively
latched into the same location until TRDY is sam-
pled asserted Only after TRDY is sampled assert-
ed is data valid in the buffer A toggling mechanism
is implemented to advance the write pointer to the
next Dword after the current Dword has been quali-
fied by TRDY
Other considerations of the partition are taken into
account on the host side as well When reading from
the buffer the command to drive the data onto the
host bus is sent before it is known that the entry is
valid This method avoids the wait-state that would
be introduced by waiting for an entry’s TRDY to be
asserted before sending the command to drive the
entry onto the host bus The FIFO structure of the
buffer also necessitates a toggling scheme to ad-
vance to the next buffer entry after the current entry
has been successfully driven Also this method
gives the LBX the ability to drive the same Dword
twice enabling reads of less than a Dword to be
serviced by the buffer reads of individual bytes of a
Dword would read the same Dword 4 times
The HIG 4 0 and PIG 3 0 lines are defined to en-
able the features described previously The LCPRF
PIG 3 0 command latches the first PCI read Dword
into the first location in the CPU-to-PCI read prefetch
buffer This command is driven until TRDY is sam-
pled asserted The valid Dword would then be in the
first location of the buffer The cycle after TRDY is
sampled asserted the PCMC drives the LCPRA
command on the PIG 3 0 lines This action latches
the value on the PCI AD 31 0 lines into the next
Dword location in the buffer Again the LCPRA com-
mand is driven until TRDY is sampled asserted
Each cycle the LCPRA command is driven data is
latched into the same location in the buffer When
TRDY is sampled asserted the PCMC drives the
LCPRB command on the PIG 3 0 lines This latches
the value on the AD 31 0 lines into the next location
in the buffer the one after the location that the previ-
ous LCPRA command latched data into After
TRDY has been sampled asserted again the com-
mand switches back to LCPRA In this way the
same location in the buffer can be filled repeatedly
until valid and when it is known that the location is
valid the next location can be filled
The commands for the HIG 4 0 CPRF CPRA and
CPRB work exactly the same way If the same com-
mand is driven the same data is driven Driving an
appropriately different command results in the next
data being driven Figure 8 illustrates the usage of
these commands
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