82433LX Datasheet, PDF (51/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
6 0 TESTABILITY
The TSCON pin may be used to help test circuits
surrounding the LBX During normal operations the
TSCON pin must be tied to VCC or connected to
VCC through a pull-up resistor All LBX outputs are
tri-stated when the TSCON pin is held low or
grounded
6 1 NAND Tree
A NAND tree is provided in the LBX for Automated
Test Equipment (ATE) board level testing The
NAND tree allows the tester to set the connectivity
of each of the LBX signal pins
The following steps must be taken to put the LBX
into PLL bypass mode and enable the NAND tree
First to enable PLL bypass mode drive RESET in-
active TEST active and the DCPWA command
(0100) on the PIG 3 0 lines Then drive PCLK from
low to high DRVPCI must be held low on all rising
edges of PCLK during testing in order to ensure that
the LBX does not drive the AD 15 0 lines The host
and memory buses are tri-stated by driving NOPM
(000) and NOPC (00000) on the MIG 2 0 and
HIG 4 0 lines and driving two rising edges on
HCLK A rising edge on PCLK with RESET high will
cause the LBXs to exit PLL bypass mode TEST
must remain high throughout the use of the NAND
tree The combination of TEST and DRVPCI high
with a rising edge of PCLK must be avoided TSCON
must be driven high throughout testing since driving
it low would tri-state the output of the NAND tree A
10 ns hold time is required on all inputs sampled by
PCLK or HCLK when in PLL bypass mode
6 1 1 TEST VECTOR TABLE
The following test vectors can be applied to the
82433LX and 82433NX to put it into PLL bypass
mode and to enable NAND tree testing
6 1 2 NAND TREE TABLE
Table 9 shows the sequence of the NAND tree in
the 82433LX and 82433NX Non-inverting inputs are
driven directly into the input of a NAND gate in the
tree Inverting inputs are driven into an inverter be-
fore going into the NAND tree The output of the
NAND tree is driven on the PPOUT pin
Table 8 Test Vectors to put LBX Into PLL Bypass and Enable NAND Tree Testing
LBX
Pin Vector
PCLK
PIG 3 0
RESET
HCLK
MIG 2 0
HIG 4 0
TEST
DRVPCI
1
2
3
4
5
6
7
8
9
10 11
0
1
0
0
1
1
1
1
1
1
1
0h 0h 0h 4h 4h 4h 4h 4h 4h 4h 4h
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h
0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
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