82433LX Datasheet, PDF (23/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
3 3 3 MIG 2 0 COMMAND
Figure 6 illustrates the timing of the MIG 2 0 com-
mands with respect to the MD bus CAS 7 0 and
WE Figure 6 shows the MD bus transitioning from
a read to a write cycle
The Latch command in Figure 6 is any of the
following
PMRFQ PMRNQ
The Retire command in Figure 6 is any of the
following
RCMWQ RPMWQ RPMWQS
The data on the MD bus is sampled at the end of the
first cycle into the LBX based on sampling the Latch
command The CAS 7 0 signals can be negated
in the next cycle The WE signal is asserted in the
next cycle The required delay between the asser-
tion of WE and the assertion of CAS 7 0 means
that the MD bus has 2 cycles to turn around hence
the NOPM command driven in the second clock
The LBX starts to drive the MD bus based on sam-
pling the Retire command at the end of the third
clock After the Retire command is driven for 1 cy-
cle the data is held at the output by the MEMDRV
command The LBX releases the MD bus based on
sampling the NOPM command at the end of the
sixth clock
Figure 6 MIG 2 0 Command Timing
290478 – 7
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