82433LX Datasheet, PDF (11/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
2 4 PCMC Interface Signals (Continued)
Signal Type
Description
EOL
t s End Of Line This signal is asserted when a PCI master read or write transaction is about
to overrun a cache line boundary The low order LBX will have this pin connected to the
PCMC (internally pulled up in the PCMC) The high order LBX connects this pin to a pull-
down resistor With one LBX EOL line being pulled down and the other LBX EOL pulled
up the LBX samples the value of this pin on the negation of the RESET signal to
determine if it’s the high or low order LBX
PPOUT t s
LBX PARITY This signal reflects the parity of the 16 AD lines driven from or latched into
the LBX depending on the command driven on PIG 3 0 The PCMC uses PPOUT from
both LBXs (called PPOUT 1 0 ) to calculate the PCI parity signal (PAR) for CPU to PCI
transactions during the address phase of the PCI cycle The LBX uses PPOUT to check
the PAR signal for PCI master transactions to memory during the address phase of the
PCI cycle When transmitting data to PCI the PCMC uses PPOUT to calculate the proper
value for PAR When receiving data from PCI the PCMC uses PPOUT to check the value
received on PAR
If the L2 cache does not implement parity the LBX will calculate parity so the PCMC can
drive the correct value on PAR during L2 reads initiated by a PCI master The LBX
samples the PPOUT signal at the negation of reset and compares that state with the state
of EOL to determine whether the L2 cache implements parity The PCMC internally pulls
down PPOUT 0 and internally pulls up PPOUT 1 The L2 supports parity if PPOUT 0 is
connected to the high order LBX and PPOUT 1 is connected to the low order LBX The
L2 is defined to not support parity if these connections are reversed and for this case the
LBX will calculate parity For normal operations either connection allows proper parity to
be driven to the PCMC
2 5 Reset and Clock Signals
Signal Type
Description
HCLK in
HOST CLOCK HCLK is input to the LBX to synchronize command and data from the host
and memory interfaces This input is derived from a buffered copy of the PCMC HCLKx
output
PCLK in
PCI CLOCK All timing on the LBX PCI interface is referenced to the PCLK input All
output signals on the PCI interface are driven from PCLK rising edges and all input signals
on the PCI interface are sampled on PCLK rising edges This input is derived from a
buffered copy of the PCMC PCLK output
RESET in
RESET Assertion of this signal resets the LBX After RESET has been negated the LBX
configures itself by sampling the EOL and PPOUT pins RESET is driven by the PCMC
CPURST pin The RESET signal is synchronous to HCLK and must be driven directly by
the PCMC
LP1
out LOOP 1 Phase Lock Loop Filter pin The filter components required for the LBX are
connected to these pins
LP2
in
LOOP 2 Phase Lock Loop Filter pin The filter components required for the LBX are
connected to these pins
TEST in
TEST The TEST pin must be tied low for normal system operation
TSCON in
TRI-STATE CONTROL This signal enables the output buffers on the LBX This pin must
be held high for normal operation If TSCON is negated all LBX outputs will tri-state
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