82433LX Datasheet, PDF (29/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
3 4 PLL Loop Filter Components
As shown in Figure 11 loop filter components are
required on the LBX components A 4 7 KX 5% re-
sistor is typically connected between pins LP1 and
LP2 Pin LP2 has a path to the PLLAGND pin
through a 100X 5% series resistor and a 0 01 mF
10% series capacitor The ground side of capacitor
C1 and the PLLVSS pin should connect to the
ground plane at a common point All PLL loop filter
traces should be kept to minimal length and should
be wider than signal traces Inductor L1 is connect-
ed to the 5V power supply on both the 82433LX and
82433NX
Some circuit boards may require filtering the power
circuit to the LBX PLL The circuit shown in Figure
11 will typically enable the LBX PLL to have higher
noise immunity than without Pin PLLVDD is con-
nected to the 5V V_CC through a 10X 5% resistor
The PLLVDD and PLLVSS pins are bypassed with a
0 01 mF 10% series capacitor
The high order 82433NX LBX samples A11 at the
falling edge of reset to configure the LBX for PLL
test mode When A11 is sampled low the LBX is in
normal operating mode When A11 is sampled high
the LBX drives the internal HCLK from the PLL on
the EOL pin Note that A11 on the high order LBX is
connected to the A27 line on the CPU address bus
This same address line is used to put the PCMC into
PLL test mode
Mercury
60 MHz
Mercury
66 MHz
Neptune
R1
4 7 KX
2 2 KX
4 7 KX
R2
100X
100X
100X
C2
0 01 mF
0 01 mF
0 01 mF
R3
10X
10X
10X
C1
0 47 mF
0 47 mF
0 47 mF
C1¹ 0 01 mF
0 01 mF
0 01 mF
Figure 11 Loop Filter Circuit
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