82433LX Datasheet, PDF (18/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
3 2 2 MEMORY INTERFACE GROUP MIG 2 0
The Memory Interface commands are shown in Table 2 These commands are issued by the DRAM controller
of the PCMC to perform the following functions
 Retires data from CPU-to-Memory Write Buffer to DRAM
 Stores data into PCI-to-Memory Read Buffer when the PCI read address is targeted to DRAM
 Retires PCI-to-Memory Write Buffer to DRAM
Table 2 MIG Commands
Command Code
Description
NOPM
000b No Operation on Memory Bus
PMRFQ 001b Place into PCI-to-Memory Read Buffer First Qword
PMRNQ 010b Place into PCI-to-Memory Read Buffer Next Qword
RCMWQ 100b Retire CPU-to-Memory Write Buffer Qword
RPMWQ 101b Retire PCI-to-Memory Write Buffer Qword
RPMWQS 110b Retire PCI-to-Memory Write Buffer Qword Shifted
MEMDRV 111b Drive Latched Data Onto Memory Bus for 1 Clock Cycle
NOTE
All other patterns are reserved
NOPMN
PMRFQ
PMRNQ
RCMWQ
RPMWQ
Operation on the memory bus The LBX
tri-states its drivers driving the memory
bus
The PCI-to-Memory read address tar-
gets memory if there is a miss on first
and second caches This command
stores the first Qword of data starting at
the first location in the buffer This buff-
er is 8 Dwords or 1 cache line deep
This command stores subsequent
Qwords from memory starting at the
next available location in the PCI-to-
Memory Read Buffer It is always used
after PMRFQ
This command retires one Qword from
the CPU-to-Memory Write Buffer to
DRAM The address is stored in the ad-
dress queue for this buffer in the
PCMC
This command retires one Qword of
data from one line of the PCI-to-Memo-
ry write buffer to DRAM When all the
valid data in one buffer is retired the
next RPMWQ (or RPMWQS) will read
data from the next buffer
RPMWQS
MEMDRV
This command retires one Qword of
data from one line of PCI-to-Memory
write buffer to DRAM For this com-
mand the data in the buffer is shifted by
one Dword (Dword in position 0 is shift-
ed to 1 1 to 2 etc ) This is because the
address targeted by the first Dword of
the write could be an odd Dword (i e
address bit 2 is a 1) To retire a misa-
ligned line this command has to be
used for all the data in the buffer When
all the valid data in one buffer is retired
the next RPMWQ (or RPMWQS) will
read data from the next buffer
For a memory write operation the data
on the memory bus is required for more
than one clock cycle hence all DRAM
retires are latched and driven to the
memory bus in subsequent cycles by
this command
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