82433LX Datasheet, PDF (16/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
NOPC
CMR
CPRF
CPRA
CPRB
CPRQ
No Operation is performed on the host
bus by the LBX hence it tri-states its
host bus drivers
This command effectively drives
DRAM data onto the host data bus
The LBX acts as a transparent latch in
this mode depending on MDLE for
latch control With the MDLE signal
high the CMR command will cause the
LBXs to buffer memory data onto the
host bus When MDLE is low The LBX
will drive onto the host bus whatever
memory data that was latched when
MDLE was negated
This command reads the first Dword of
the CPU-to-PCI read prefetch buffer
The read pointer of the FIFO is set to
point to the first Dword The Dword is
driven onto the high and low halves of
the host data bus
This command increments the read
pointer of the CPU-to-PCI read pre-
fetch buffer FIFO and drives that
Dword onto the host bus when it is
driven after a CPRF or CPRB com-
mand If driven after another CPRA
command the LBX drives the current
Dword while the read pointer of the
FIFO is not incremented The Dword is
driven onto the upper and lower halves
of the host data bus
This command increments the read
pointer of the CPU-to-PCI read pre-
fetch buffer FIFO and drives that
Dword onto the host bus when it is
driven after a CPRA command If driv-
en after another CPRB command the
LBX drives the current Dword while the
read pointer of the FIFO is not incre-
mented The Dword is driven onto the
upper and lower halves of the host
data bus
This command drives the first Dword
stored in the CPU-to-PCI read prefetch
buffer onto the lower half of the host
data bus and drives the second Dword
onto the upper half of the host data
bus regardless of the state of the read
pointer The read pointer is not affect-
ed by this command
SWB0
SWB1
SWB2
SWB3
PCMWQ
PCMWFQ
PCMWNQ
This command stores a Qword from
the host data lines into location 0 of
the PCI-to-Memory Read Buffer Parity
is either generated for the data or prop-
agated from the host bus based on the
state of the PPOUT signals sampled at
the negation of RESET when the LBXs
were initialized
This command (similar to SWB0)
stores a Qword from the host data
lines into location 1 of the PCI-to-Mem-
ory Read Buffer Parity is either gener-
ated from the data or propagated from
the host bus based on the state of the
PPOUT signal sampled at the falling
edge of RESET
This command (similar to SWB0)
stores a Qword written back from the
first or second level cache into location
2 of the PCI-to-memory read buffer
Parity is either generated from the data
or propagated from the host bus based
on the state of the PPOUT signal sam-
pled at the falling edge of RESET
This command stores a Qword from
the host data lines into location 3 of
the PCI-to-Memory Read Buffer Parity
is either generated for the data or prop-
agated from the host bus based on the
state of the PPOUT signal sampled at
the falling edge of RESET
This command posts one Qword of
data from the host data lines to CPU-
to-Memory Write Buffer in case of a
CPU memory write or a write-back from
the second level cache
If the PCI Memory read address leads
to a hit on a modified line in the first
level cache then a write-back is
scheduled and this data has to be writ-
ten into the CPU-to-Memory Write Buff-
er and PCI-to-Memory Read Buffer at
the same time The write-back of the
first Qword is done by this command to
both the buffers
This command follows the previous
command to store or post subsequent
write-back Qwords
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