82433LX Datasheet, PDF (13/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
completely to the CPU-to-Memory posted Write
Buffer
If the PCI master read data is read from the second-
ary cache it is not written back to memory Write-
backs from the second level cache when using
burst SRAMs are in Pentium processor burst order
(the order depending on which Qword of the line is
targeted by the PCI read) The buffer is directly ad-
dressed when latching second level cache write-
back data to accommodate this burst order For ex-
ample if the requested Qword is Qword 1 then the
burst order is 1-0-3-2 Qword 1 is latched in buffer
location 0 Qword 0 is discarded Qword 3 is latched
into buffer location 2 and Qword 2 is latched into
buffer location 1
Commands driven on MIG 2 0 and HIG 4 0 enter
data into the buffer from the DRAM interface and the
host interface (i e the caches) respectively Com-
mands driven on the PIG 3 0 lines drive data from
the buffer onto the PCI AD 31 0 lines
Parity driven on the PPOUT signal is calculated from
the byte parity received on the host bus or the mem-
ory bus whichever is the source If the second level
cache is the source of the data and does not imple-
ment parity the parity driven on PPOUT is generated
by the LBX from the second level cache data If
main memory is the source of the read data PCI
parity is calculated from the DRAM byte parity Main
memory must implement byte parity to guarantee
correct PCI parity generation
3 1 4 CPU-TO-PCI POSTED WRITE BUFFER
The CPU-to-PCI Posted Write Buffer is 4 Dwords
deep The buffer is constructed as a simple FIFO
with some performance enhancements An address
is stored in the LBX with each Dword of data The
structure of the buffer accommodates the packetiza-
tion of writes to be burst on PCI This is accom-
plished by effectively discarding addresses of data
Dwords driven within a burst Thus while an address
is stored for each Dword an address is not neces-
sarily driven on PCI for each Dword The PCMC de-
termines when a burst write may be performed
based on consecutive addresses The buffer also
enables consecutive bytes to be merged within a
single Dword accommodating byte word and misa-
ligned Dword string store and string move opera-
tions Qword writes on the host bus are stored within
the buffer as two individual Dword writes with sepa-
rate addresses
The storing of an address with each Dword of data
allows burst writes to be retried easily In order to
retry transactions the FIFO is effectively ‘‘backed
up’’ by one Dword This is accomplished by making
the FIFO physically one entry larger than it is logical-
ly Thus the buffer is physically 5 entries deep (an
entry consists of an address and a Dword of data)
while logically it is considered full when 4 entries
have been posted This design allows the FIFO to
be backed up one entry when it is logically full
Commands driven on HIG 4 0 post addresses and
data into the buffer and commands driven on
PIG 3 0 retire addresses and data from the buffer
and drive them onto the PCI AD 31 0 lines As dis-
cussed previously when bursting not all addresses
are driven onto PCI
Data parity driven on the PPOUT signal is calculated
from the byte parity received on the host bus Ad-
dress parity driven on PPOUT is calculated from the
address received on the host bus
13