82433LX Datasheet, PDF (7/53 Pages) Intel Corporation – LOCAL BUS ACCELERATOR (LBX)

82433LX 82433NX
1 2 Control Interface Groups
The LBX is controlled by the PCMC via the control
interface group signals There are three interface
groups Host Memory and PCI These control
groups are signal lines that carry binary codes which
the LBX internally decodes in order to implement
specific functions such as latching data and steering
data from PCI to memory The control interfaces are
described below
1 Host Interface Group These control signals are
named HIG 4 0 and define a total of 29 (30 for
the 82433NX) discrete commands The PCMC
sends HIG commands to direct the LBX to per-
form functions related to buffering and storing
host data and or address
2 Memory Interface Group These control signals
are named MIG 2 0 and define a total of 7 dis-
crete commands The PCMC sends MIG com-
mands to direct the LBX to perform functions re-
lated to buffering storing and retiring data to
memory
3 PCI Interface Group These control signals are
named PIG 3 0 and define a total of 15 discrete
commands The PCMC sends PIG commands to
direct the LBX to perform functions related to
buffering and storing PCI data and or address
1 3 System Bus Interconnect
The architecture of the 82430 82430NX PCIset
splits the 64-bit memory and host data buses into
logical halves in order to manufacture LBX devices
with manageable pin counts The two LBXs interface
to the 32-bit PCI AD 31 0 bus with 16 bits each
Each LBX connects to 16 bits of the AD 31 0 bus
and 32-bits of both the MD 0 63 bus and the
D 0 63 bus The lower order LBX (LBXL) connects
to the low word of the AD 31 0 bus while the high
order LBX (LBXH) connects to the high word of the
AD 31 0 bus
Since the PCI connection for each LBX falls on
16-bit boundaries each LBX does not simply con-
nect to either the low Dword or high Dword of the
Qword memory and host buses Instead the low or-
der LBX buffers the first and third words of each
64-bit bus while the high order LBX buffers the sec-
ond and fourth words of the memory and host
buses
As shown in Figure 2 LBXL connects to the first and
third words of the 64-bit main memory and host data
buses The same device also drives the first 16 bits
of the host address bus A 15 0 The LBXH device
connects to the second and fourth words of the
64-bit main memory and host data buses Corre-
spondingly LBXH drives the remaining 16 bits of the
host address bus A 31 16
290478 – 3
Figure 2 Simplified Interconnect Diagram of LBXs to System Buses
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