English
Language : 

X9000 Datasheet, PDF (7/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process
Introduction
1
Note:
Introduction
The Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor built on 45-
nanometer process technology are the next generation high-performance, low-power
mobile processors based on the Intel® Core™ microarchitecture. The Intel Core 2 Duo
processor and Intel Core 2 Extreme processor support the Mobile Intel® 965 Express
Chipset and Intel® 82801HBM ICH8 Controller Hub-Based Systems. The document
contains electrical, mechanical and thermal specifications for the following processors:
• Intel Core 2 Duo processor - Standard Voltage
• Intel Core 2 Extreme processor
In this document, the Intel Core 2 Duo processor and Intel Core 2 Extreme mobile
processor built on 45-nm process technology are referred to as the processor. The
Mobile Intel® 965 Express Chipset family is referred to as the (G)MCH.
The following list provides some of the key features on this processor:
• Dual-core processor for mobile with enhanced performance.
• Supports Intel® architecture with Intel® Wide Dynamic Execution.
• Supports L1 cache-to-cache (C2C) transfer.
• Supports PSI2 functionality.
• Supports Enhanced Intel® Virtualization Technology.
• On-die, primary 32-KB instruction cache and 32-KB write-back data cache in each
core.
• On-die, up to 6-MB second-level shared cache with Advanced Transfer Cache
Architecture.
• Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3),
Supplemental Streaming SIMD Extensions 3 (SSSE3) and SSE4.1 Instruction Sets.
• 800-MHz Source-Synchronous front side bus (FSB).
• Advanced power management features including Enhanced Intel SpeedStep®
Technology and Dynamic FSB frequency switching.
• Digital Thermal Sensor (DTS).
• Intel® 64 architecture.
• Intel® Dynamic Acceleration Technology and Enhanced Multi-Threaded Thermal
Management (EMTTM).
• Micro-FCPGA and Micro-FCBGA packaging technologies (Extreme Edition only
available in Micro-FCPGA).
• Execute Disable Bit support for enhanced security.
• Deep Power-Down Technology with P_LVL6 I/O Support.
• Half-ratio support (N/2) for Core-to-Bus ratio.
Datasheet
7