X9000 Datasheet, PDF (28/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Electrical Specifications
Table 4.
FSB Pin Groups
Signal Group
Type
AGTL+ Common Clock
Input
Synchronous
to BCLK[1:0]
AGTL+ Common Clock I/O
Synchronous
to BCLK[1:0]
Signals¹
BPRI#, DEFER#, PREQ#⁵, RESET#, RS[2:0]#,
TRDY#
ADS#, BNR#, BPM[3:0]#³, BR0#, DBSY#,
DRDY#, HIT#, HITM#, LOCK#, PRDY#³, DPWR#
AGTL+ Source
Synchronous I/O
Synchronous
to assoc.
strobe
Signals
Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[35:17]#
ADSTB[1]#
D[15:0]#, DINV0# DSTBP0#, DSTBN0#
D[31:16]#, DINV1# DSTBP1#, DSTBN1#
D[47:32]#, DINV2# DSTBP2#, DSTBN2#
D[63:48]#, DINV3# DSTBP3#, DSTBN3#
AGTL+ Strobes
CMOS Input
Open Drain Output
Open Drain I/O
CMOS Output
CMOS Input
Open Drain Output
FSB Clock
Power/Other
Synchronous
to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#,
Asynchronous LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#,
STPCLK#
Asynchronous FERR#, IERR#, THERMTRIP#
Asynchronous PROCHOT#⁴
Asynchronous PSI#, VID[6:0], BSEL[2:0]
Synchronous
to TCK
TCK, TDI, TMS, TRST#
Synchronous
to TCK
TDO
Clock
BCLK[1:0]
COMP[3:0], DBR#², GTLREF, RSVD, TEST2,
TEST1, THERMDA, THERMDC, V_CC, V_CCA, V_CCP,
V_{CC_SENSE}, V_SS, V_{SS_SENSE}
NOTES:
1.
Refer to Chapter 4 for signal descriptions and termination requirements.
2.
In processor systems where there is no debug port implemented on the system board,
these signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no-connects.
3.
BPM[2:1]# and PRDY# are AGTL+ output-only signals.
4.
PROCHOT# signal type is open drain output and CMOS input.
5.
On-die termination differs from other AGTL+ signals.
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Datasheet