X9000 Datasheet, PDF (23/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Electrical Specifications
3 Electrical Specifications
3.1
3.2
3.3
Table 2.
Power and Ground Pins
For clean, on-chip power distribution, the processor will have a large number of V_CC
(power) and V_SS (ground) inputs. All power pins must be connected to V_CC power
planes while all V_SS pins must be connected to system ground planes. Use of multiple
power and ground planes is recommended to reduce I*R drop. Refer to the platform
design guide for more details. The processor V_CC pins must be supplied the voltage
determined by the VID (Voltage ID) pins.
FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous-generation processors, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor uses a differential clocking
implementation.
Voltage Identification
The processor uses seven voltage identification pins,VID[6:0], to support automatic
selection of power supply voltages. The VID pins for processor are CMOS outputs
driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding
to the state of VID[6:0]. A 1 refers to a high-voltage level and a 0 refers to low-voltage
level.
Voltage Identification Definition (Sheet 1 of 4)
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V_CC (V)
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2875
Datasheet
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