X9000 Datasheet, PDF (65/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 4 of 8)
Name
Type
Description
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]#
Input/
Output
Signals
D[15:0]#, DINV[0]#
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
Associated Strobe
DSTBP[0]#
DSTBP[1]#
DSTBP[2]#
DSTBP[3]#
FERR#/PBE#
GTLREF
HIT#
HITM#
IERR#
Output
Input
Input/
Output
Input/
Output
Output
FERR# (Floating-point Error)/PBE#(Pending Break Event) is a
multiplexed signal and its meaning is qualified with STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating point
when the processor detects an unmasked floating-point error.
FERR# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting. When STPCLK# is
asserted, an assertion of FERR#/PBE# indicates that the processor
has a pending break event waiting for service. The assertion of
FERR#/PBE# indicates that the processor should be returned to the
Normal state. When FERR#/PBE# is asserted, indicating a break
event, it will remain asserted until STPCLK# is deasserted.
Assertion of PREQ# when STPCLK# is active will also cause an
FERR# break event.
For additional information on the pending break event functionality,
including identification of support of the feature and enable/disable
information, refer to Volumes 3A and 3B of the Intel® 64 and IA-32
Architectures Software Developer's Manuals and the CPUID
Instruction Application Note.
Refer to the appropriate platform design guide for termination
requirements.
GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 V_CCP. GTLREF is used by the AGTL+
receivers to determine if a signal is a Logical 0 or Logical 1.
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Either FSB agent may assert both HIT#
and HITM# together to indicate that it requires a snoop stall that
can be continued by reasserting HIT# and HITM# together.
IERR# (Internal Error) is asserted by the processor as the result of
an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the FSB. This transaction may optionally
be converted to an external error signal (e.g., NMI) by system core
logic. The processor will keep IERR# asserted until the assertion of
RESET#, BINIT#, or INIT#.
Datasheet
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