X9000 Datasheet, PDF (33/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Electrical Specifications
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
2.
The voltage specifications are assumed to be measured across V_{CC_SENSE} and V_{SS_SENSE} pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
Specified at 105°C T_J.
4.
Specified at the nominal V_CC.
5.
Measured at the bulk capacitors on the motherboard.
6.
V_CC,BOOT tolerance shown in Figure 5 and Figure 6.
7.
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal V_CC. Not 100% tested.
8.
This is a power-up peak current specification that is applicable when V_CCP is high and V_{CC_CORE} is low.
9.
This is a steady-state Icc current specification that is applicable when both V_CCP and V_{CC_CORE} are high.
10. Processor I_CC requirements in Intel Dynamic Acceleration Technology mode is lesser than I_CC in HFM
11. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
equal to 300 mV.
12. Instantaneous current I_{CC_CORE_INST} of 55 A has to be sustained for short time (t_INST) of 10 µs. Average
current will be less than maximum specified I_CCDES. VR OCP threshold should be high enough to support
current levels described herein.
Figure 5. Active V_CC and I_CC Loadline Standard Voltage and Extreme Edition Processors
VCC-CORE max {HFM|LFM}
VCC-CORE, DC max {HFM|LFM}
VCC-CORE nom {HFM|LFM}
V_CC-CORE [V]
Slope = -2.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
10mV= RIPPLE
VCC-CORE, DC min {HFM|LFM}
VCC-CORE min {HFM|LFM}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
I_CC-CORE
0
ICC-CORE max
[A]
{HFM|LFM}
Note 1/ VCC-CORE Set Point Error Tolerance is per below :
Tolerance VCC-CORE VID Voltage Range
--------------- --------------------------------------------------------
+/-1.5%
VCC-CORE > 0.7500V
+/-11.5mV 0.5000V </= Vcc_core </= 0.75000V
Datasheet
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