X9000 Datasheet, PDF (12/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Low Power Features
Figure 1. Core Low-Power States
C1/
MWAIT
Stop
Grant
STPCLK#
asserted
STPCLK#
de-asserted
STPCLK#
STPCLK#
de-asserted
STPCLK# ^asserted
de-asserted
STPCLK#
asserted
Core state
break
HLT instruction
C1/Auto
Halt
MWAIT(C1)
C4^{† ‡}/C6
Core State
break
P_LVL4 or
ø
P_LVL5/P_LVL6
MWAIT(C4/C6)
Halt break
C0
P_LVL2 or
MWAIT(C2)
Core state
break
P_LVL3 or
CoreMWAIT(C3)
state
break
C2^†
C3^†
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
† — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.
‡ — Core C4 state supports the package level Intel Enhanced Deeper Sleep state.
Ø — P_LVL5/P_LVL6 read is issued once the L2 cache is reduced to zero.
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Datasheet